ADC research trends: Endangered performance parameters

Figure 1. Fraction of papers reporting a specific parameter.

SCIENTIFIC PRACTICES: In the previous post, your opinions on which parameters should be mandatory in an A/D-converter implementation paper were surveyed through a poll. In this one we will see what parameters actually get reported in scientific papers, and how the overall reporting practices have changed over time. We can also try to see how well Converter Passion reader’s opinions are in sync with harsh scientific reality

Working with the ADC survey, I had noticed that the set of measured performance parameters authors choose to report or omit changed over time. I’ve gathered the statistics, and it will be interesting to hear what you think of it. Figure 1 shows the percentage of papers reporting signal-to-noise-and-distortion ratio (SNDR), signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR) and total harmonic distortion (THD) each year. The good news is that dynamic single-tone performance is more frequently reported in today’s papers than ever before. In fact, SNDR was reported in 96% of all papers from 2011. Both SNDR and SFDR show noisy but steadily increasing trends, and SFDR is now reported in around 68% of all papers (2011).

At the same time, SNR is increasingly being abandoned in favor of simply reporting SNDR instead. We can also see that THD is becoming an endangered parameter. SNR and THD have been in a visible decline after year 2000, and THD was only reported in 12% of the papers in 2011. SNR went from 60% in year 2000 to 41% 2011. These numbers trouble me. If the trend continues, we will know less about the noise in our A/D-converters for each year. I can’t possibly see how that can be of benefit to “Science” or to the reader. If you can, be sure to post a comment below.

Figure 2. Fraction of papers reporting specific combinations of parameters.

Above we looked at the reporting frequency for each individual parameter. Authors also choose which simultaneous combination or set of performance parameters they include in a paper. This is shown in Fig. 2. Many works report SNDR together with SFDR, and 67% of all papers from 2011 reported at least these two parameters. There is a strong positive trend, so within a decade we may see SNDR+SFDR reported in nearly all published papers. The second most popular parameter pair is SNDR+SNR, with 38% coverage in 2011. Unfortunately, its reporting frequency is limited by the negative trend for SNR.

A more complete single-tone characterization is achieved with the three-parameter combination SNDR+SNR+SFDR. Only 21% of all papers published in 2011 offer this much information about the circuit. Even if there is currently a positive trend, it might soon become limited by the decline in SNR reporting, and eventually reverse.

The practice to report a full four-parameter set is very unusual – only 9% of the papers did that in 2011. It has actually never been really common, and if THD continues to disappear from papers, the four-parameter performance will be increasingly rare. Lots of credit to authors that are still reporting a full set! It is much appreciated here at Converter Passion.

Rare species

Finally, a few other rare species in the ADC parameter ecosystem are shown in Fig. 3. While the highly valuable parameter self-noise appears to be on its way to extinction, intermodulation distortion (IMD) as represented by the second- and third-order intercept point (IP2, IP3) seems to cling to life in the outskirts of the habitat.

So … what do you make of all this? Do you think it will have any long-term impact on our field of science? Does it matter to you what parameters are reported or not? Have your say in the comments below.

And, what happened around year 2000 to shift the trends so dramatically? Was it the dot-com boom or the Y2K bug? (I haven’t heard about that one for a while now)

Figure 3. Endangered species in the parameter ecosystem.

Poll result: What parameters should be mandatory in ADC papers?

Poll: What ADC parameters should be mandatory in ADC implementation papers?

Back in July 2011, I raised the question “What parameters should be reported in a good ADC paper?”, and I also asked you what parameters you felt should be mandatory to report in ADC implementation type of papers, when applicable. The poll has been simmering for a while now, and your verdict as of May 28, 2012 is shown above.

Sampling rate (or bandwidth) is the parameter that most of the voters felt should be mandatory to report, closely followed by signal-to-noise-and-distortion ratio (SNDR). I kind of expected these two to come out on top. The lowest ranking parameters in this poll are effective resolution bandwidth (ERBW), self-noise, and intermodulation distortion (IMD).

There are some results that surprised me: I didn’t expect to see the low interest in nominal ADC resolution (N) and power dissipation (P). Only half of the voters want to require authors to report power dissipation, and as little as one third (!) wish to enforce the reporting of nominal resolution when applicable. Interesting, indeed.

What do you say? Are these results expected? Does the ranking list match your personal parameter preferences as well? Are your top two parameters also fs and SNDR (ENOB)?

I’ll keep the poll active, so if you want to have a say too, just make your choices below.

ADC research trends: Overall publication count

The exponential growth in ADC publications

PUBLICATION TRENDS: Now, with all the new survey data, I’m planning to do a series of posts on A/D-converter performance evolution and research trends. First out is an update of the overall number-of-publications trend, which was originally discussed in one of the first post on the blog.

The graph shows the total number of ADC implementation papers per year in the sources listed here. The y-axis is logarithmic to simplify observation of exponential trends. My interpretation is that publication count follows a consistent exponential trend from 1988 and onwards. A log-fit of the data between 1988 and 2011 reveals that the number of A/D-converter papers have doubled approximately every decade since 1988, and that the annual increase is 6.8%. For anyone interested, the expression for the trend line is

If the scientific output volume follows the current trend, it projects to 225 ADC papers per year by 2020 and 433 papers in year 2030. That’s a lot of papers! Probably we’ll see a slow-down in publication volume before that, but only the future can tell us when, and to what level it will saturate. It is possible that we’re already observing a saturation towards ~120 papers/year. The paper count has not increased since 2008. On the other hand, the historical curve is not monotonic, so it could just as well be noise in the data. A similar four-year plateau is for example observed 1996-1999, without changing the overall trend.

What do you think? Are we observing a saturation of the scientific ADC output volume? Would that be good or bad? Is there a limit for how many papers the ADC community can handle per year? Share your thoughts or answer the polls.

 

Here’s an old poll which is still active:

Australia’s first scientific ADC

Congratulations!

BREAKING NEW GROUND: The ADC landscape is continuously changing – also geographically. To the best of my knowledge, 2012 is the year when Australia became the 30^th nation to successfully implement, measure, and scientifically report, an A/D-converter IC (*). Great news!

Authors Jeffrey Harrison, Michal Nesselroth, Robert Mamuad, Arya Behzad, Andrew Adams, and Steve Avery presented their design in the ISSCC contribution “An LC Bandpass ΔΣ ADC with 70dB SNDR Over 20MHz Bandwidth Using CMOS DACs” [1].

The organization behind this Australian milestone is Broadcom. Arya Behzad is affiliated with Broadcom, San Diego, CA. All other authors are with Broadcom, Sydney, Australia. Excellent job!

Reference

[1] J. Harrison, M. Nesselroth, R. Mamuad, A. Behzad, A. Adams, and S. Avery, “An LC Bandpass ΔΣ ADC with 70dB SNDR Over 20MHz Bandwidth Using CMOS DACs,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 146–147, Feb., 2012.

Footnote

(*) NB: The definition I use is first-author-centric. It looks only at the country of the 1st-author affiliation. It is also focused on the accumulated scientific output of the sources listed here. If you are aware of an earlier Australian ADC implementation, please let me know.

ADC Survey: Spring 2012 update on FOM state-of-the-art

Will reading tons of ADC papers grow your brain — or wear it out?

Well folks, its the time of year when an A/D-converter survey update is due. Since a significant effort is still invested in the quest for ever-improving figures-of-merit (FOM), I’ll start by firing up the Converter Passion FOM-o-meter  and apply it to the body of ADC science. The latter is here approximated by my pet project – the ADC performance survey.

Including the papers added since last year, the updated survey now has 3628 experimental data points extracted from 1708 scientific papers published between 1974 and April/May 2012. The number of unique ADC implementations will be slightly less, since some papers are full-length versions of conference contributions. The source publications monitored are listed here.

What a difference a year makes …

… or not?

ISSCC/Walden-FOM

Can you believe this: With all the current competition to get a great ISSCC/Walden-FOM

the state-of-the-art (4.4 fJ) reported by van Elzakker et al. at ISSCC four years ago [1] is still number one. Their design really went the extra mile with respect to getting a low energy per sample, and I guess that paid off big time. Well done!

As Michiel commented, it is just a matter of time before someone goes below 4.4 fJ. This is also reflected in the scientific output over the last twelve months. Although the current world record didn’t change, there are several designs that reported an < 10 fJ, and that’s not bad either. They are:

FOM [fJ]	Speed [S/s]	ENOB	Architecture	1st Author	Ref
8.7	2M	8.27	SAR	Sekimoto	[2]
6.8	1k	8.52	SAR	Lu	[3]
6.5	4M	9.4	SAR	Harpe	[4]
6.1	1.1M	7.48	SAR	Shikata	[5]
6.8	10M	10.0	SAR	Verbruggen	[6]
9.7	250M	9.45	SAR	Verbruggen	[6]

The most striking feature is probably that they are all SAR ADCs. Secondly, while they are all impressive efforts, the one that stands out a bit is the design by Verbruggen et al. It maintains a sub-10fJ FOM at a significantly higher sampling rate (250 MS/s) while also reporting the highest resolution [6].

Although it’s beyond the scope of this post, it can be good to keep in mind that there are other aspects to factor in than simply the FOM value when analyzing energy efficiency. It was pointed out by Verbruggen [6] that previous ultra-low FOM ADCs have been reported only at rather low sampling rates or moderate resolution. It is a greater challenge to maintain a low for high sampling rates. Hence, pragmatic limits to the state-of-the-art are speed-dependent. It has also been shown that the limits are both scaling- and resolution-dependent [7, 8], so a perfectly fair comparison between designs is difficult to make. I can pretty much guarantee that I’ll get back to this topic in the future, but for the remainder of this post we’ll just look at the raw FOM numbers as they are.

Thermal FOM

It would have been boring to read another 100+ papers and still have nothing new to report, so I’m very glad to see that the so called “Thermal FOM”

has been improved by over a factor of two through the switched-opamp (SO) based ∆∑ design reported by Xu et al. [9]. Previous state-of-the-art – 2.7aJ reported by Perez et al. [10] – will assume its well-earned place in the Hall of Fame, while we applaud the 1.1 aJ achieved by the Chinese team from Zheijan University and Analog Devices, Shanghai. You’re the best now. Enjoy!

Thermal FOM for Nyquist ADCs

There has also been some evolution among the Nyquist ADCs: The 250MS/s SAR ADC by Verbruggen et al. mentioned above, is actually the new Thermal-FOM champion for Nyquist ADCs as it nudges the previous record [11] from 7.6 to 6.6 aJ. The authors are with imec, Belgium, and Renesas Electronics, Japan. Congratulations!

Old and new winners are always found in the halls of fame for Thermal and Walden FOM, respectively. If you are only interested in checking for the current leaders, the FOM-o-meter gives you both with a single click.

As always: I do believe the information here is correct, but if I’ve misrepresented anyone or forgotten to mention someone that should have been included, just send me an email or post a comment below.

References

[1] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.

[2] R. Sekimoto, A. Shikata, T. Kuroda, and H. Ishikuro, “A 40nm 50S/s – 8MS/s Ultra Low Voltage SAR ADC with Timing Optimized Asynchronous Clock Generator,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Helsinki, Finland, pp. 471–474, Sept., 2011.

[3] T.-C. Lu, L.-D. Van, C.-S. Lin, C.-M. Huang, “A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/Conversion-Step SAR ADC for Biomedical Applications,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.

[4] P. Harpe, Y. Zhang, G. Dolmans, K. Philips, and H. De Groot, “A 7-to-10b 0-to-4MS/s Flexible SAR ADC with 6.5-to-16fJ/conversion-step,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 472–473, Feb., 2012.

[5] A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS,” IEEE J. Solid-State Circuits, Vol. 47, pp. 1022–1030, Apr., 2012.

[6] B. Verbruggen, M. Iriguchi, and J. Craninckx, “A 1.7mW 11b 250MS/s 2× Interleaved Fully Dynamic Pipelined SAR ADC in 40nm Digital CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 466–467, Feb., 2012.

[7] B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.

[8] B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, June 2011.

[9] J. Xu, X. Wu, M. Zhao, R. Fan, H. Wang, X. Ma, and B. Liu, “Ultra Low-FOM High-Precision ΔΣ Modulators with Fully-Clocked SO and Zero Static Power Quantizers,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.

[10] A. P. Perez, E. Bonizzoni, and F. Maloberti, “A 84dB SNDR 100kHz Bandwidth Low-Power Single Op-Amp Third-Order ΔΣ Modulator Consuming 140μW,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, USA, pp. 478-480, Feb., 2011.

[11] C. P. Hurrell, C. Lyden, D. Laing, D. Hummerston, and M. Vickery, “An 18 b 12.5 MS/s ADC With 93 dB SNR,” IEEE J. Solid-State Circuits, Vol. 45, pp. 2647-2654, Dec., 2010.