ADC Survey: Spring 2012 update on FOM state-of-the-art

Will reading tons of ADC papers grow your brain — or wear it out?

Well folks, its the time of year when an A/D-converter survey update is due. Since a significant effort is still invested in the quest for ever-improving figures-of-merit (FOM), I’ll start by firing up the Converter Passion FOM-o-meter  and apply it to the body of ADC science. The latter is here approximated by my pet project – the ADC performance survey.

Including the papers added since last year, the updated survey now has 3628 experimental data points extracted from 1708 scientific papers published between 1974 and April/May 2012. The number of unique ADC implementations will be slightly less, since some papers are full-length versions of conference contributions. The source publications monitored are listed here.

What a difference a year makes …

… or not?

ISSCC/Walden-FOM

Can you believe this: With all the current competition to get a great ISSCC/Walden-FOM

the state-of-the-art (4.4 fJ) reported by van Elzakker et al. at ISSCC four years ago [1] is still number one. Their design really went the extra mile with respect to getting a low energy per sample, and I guess that paid off big time. Well done!

As Michiel commented, it is just a matter of time before someone goes below 4.4 fJ. This is also reflected in the scientific output over the last twelve months. Although the current world record didn’t change, there are several designs that reported an < 10 fJ, and that’s not bad either. They are:

FOM [fJ]	Speed [S/s]	ENOB	Architecture	1st Author	Ref
8.7	2M	8.27	SAR	Sekimoto	[2]
6.8	1k	8.52	SAR	Lu	[3]
6.5	4M	9.4	SAR	Harpe	[4]
6.1	1.1M	7.48	SAR	Shikata	[5]
6.8	10M	10.0	SAR	Verbruggen	[6]
9.7	250M	9.45	SAR	Verbruggen	[6]

The most striking feature is probably that they are all SAR ADCs. Secondly, while they are all impressive efforts, the one that stands out a bit is the design by Verbruggen et al. It maintains a sub-10fJ FOM at a significantly higher sampling rate (250 MS/s) while also reporting the highest resolution [6].

Although it’s beyond the scope of this post, it can be good to keep in mind that there are other aspects to factor in than simply the FOM value when analyzing energy efficiency. It was pointed out by Verbruggen [6] that previous ultra-low FOM ADCs have been reported only at rather low sampling rates or moderate resolution. It is a greater challenge to maintain a low for high sampling rates. Hence, pragmatic limits to the state-of-the-art are speed-dependent. It has also been shown that the limits are both scaling- and resolution-dependent [7, 8], so a perfectly fair comparison between designs is difficult to make. I can pretty much guarantee that I’ll get back to this topic in the future, but for the remainder of this post we’ll just look at the raw FOM numbers as they are.

Thermal FOM

It would have been boring to read another 100+ papers and still have nothing new to report, so I’m very glad to see that the so called “Thermal FOM”

has been improved by over a factor of two through the switched-opamp (SO) based ∆∑ design reported by Xu et al. [9]. Previous state-of-the-art – 2.7aJ reported by Perez et al. [10] – will assume its well-earned place in the Hall of Fame, while we applaud the 1.1 aJ achieved by the Chinese team from Zheijan University and Analog Devices, Shanghai. You’re the best now. Enjoy!

Thermal FOM for Nyquist ADCs

There has also been some evolution among the Nyquist ADCs: The 250MS/s SAR ADC by Verbruggen et al. mentioned above, is actually the new Thermal-FOM champion for Nyquist ADCs as it nudges the previous record [11] from 7.6 to 6.6 aJ. The authors are with imec, Belgium, and Renesas Electronics, Japan. Congratulations!

Old and new winners are always found in the halls of fame for Thermal and Walden FOM, respectively. If you are only interested in checking for the current leaders, the FOM-o-meter gives you both with a single click.

As always: I do believe the information here is correct, but if I’ve misrepresented anyone or forgotten to mention someone that should have been included, just send me an email or post a comment below.

References

[1] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.

[2] R. Sekimoto, A. Shikata, T. Kuroda, and H. Ishikuro, “A 40nm 50S/s – 8MS/s Ultra Low Voltage SAR ADC with Timing Optimized Asynchronous Clock Generator,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Helsinki, Finland, pp. 471–474, Sept., 2011.

[3] T.-C. Lu, L.-D. Van, C.-S. Lin, C.-M. Huang, “A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/Conversion-Step SAR ADC for Biomedical Applications,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.

[4] P. Harpe, Y. Zhang, G. Dolmans, K. Philips, and H. De Groot, “A 7-to-10b 0-to-4MS/s Flexible SAR ADC with 6.5-to-16fJ/conversion-step,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 472–473, Feb., 2012.

[5] A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS,” IEEE J. Solid-State Circuits, Vol. 47, pp. 1022–1030, Apr., 2012.

[6] B. Verbruggen, M. Iriguchi, and J. Craninckx, “A 1.7mW 11b 250MS/s 2× Interleaved Fully Dynamic Pipelined SAR ADC in 40nm Digital CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 466–467, Feb., 2012.

[7] B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.

[8] B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, June 2011.

[9] J. Xu, X. Wu, M. Zhao, R. Fan, H. Wang, X. Ma, and B. Liu, “Ultra Low-FOM High-Precision ΔΣ Modulators with Fully-Clocked SO and Zero Static Power Quantizers,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.

[10] A. P. Perez, E. Bonizzoni, and F. Maloberti, “A 84dB SNDR 100kHz Bandwidth Low-Power Single Op-Amp Third-Order ΔΣ Modulator Consuming 140μW,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, USA, pp. 478-480, Feb., 2011.

[11] C. P. Hurrell, C. Lyden, D. Laing, D. Hummerston, and M. Vickery, “An 18 b 12.5 MS/s ADC With 93 dB SNR,” IEEE J. Solid-State Circuits, Vol. 45, pp. 2647-2654, Dec., 2010.

The path to a good A/D-converter FOM

Figure 1. ENOB, power, and sampling rate trajectories showing the evolution path to the current state-of-the art FOM.

If you are participating in the scientific competition to report an ever better ADC figure-of-merit (FOM), you will find some pretty useful information in this post. Basically it will tell you where to start “drilling for oil”, and with a bit of persistence (preferably combined with some skill in the art) it might take you all the way to ISSCC 2013. The deadline for ISSCC 2012 is probably a bit too close for anyone to make a full ADC implementation according to these guidelines and still get it back in time from the foundry. But you can always try. I will give you a set of information about design and performance parameters that will enable you to predict quite accurately where in the design space the next state-of-the-art ADC (with respect to FOM) will be located. Remember that it could be your ADC, if you choose to optimize the speed-resolution-power tradeoff for this particular target.

First, let us clarify that we are talking about the most commonly used ADC figure-of-merit of all:

Figure 1 illustrates the trajectories of each of the three parameters in F_A1 as F_A1 improved over time. Click on the image to enlarge it. Only the data points representing an advance of F_A1 state-of-the-art, i.e., the monotonic decrease of F_A1 over time are used in the plot. Time was also quantized so that only the single best ADC per year appears in the trajectories. The underlying data set is gathered from 1600 scientific papers, and the same as used in [1]-[5]. The FOM axis and the FOM values for each dot are the same for all three plots, while the x axes show the simultaneous values of ENOB, power dissipation and sampling rate, respectively. These are the three parameters used to calculate the FOM, so any systematic trends in their trajectories are likely to be a good direction for a FOM-optimized design.

Figure 2. Approximate trajectory trends suggested by the plots.

Although there is plenty of noise in some of the trajectories, visual inspection suggests the approximate trends indicated in Fig. 2. At least it is my best guesstimate. It is purely ad hoc, and you are of course invited to discuss and refine my estimates by posting comments below. The most obvious trend applies to power dissipation (P), which has reduced by almost six orders of magnitude – from Watts to micro-Watts. At the same time the effective resolution (ENOB) has followed a more noisy, but visible path towards lower (medium) resolutions – from ~14 to currently 9-b ENOB. The change equals a three orders of magnitude increase in error power. Finally, the sampling rates at which state-of-the-art figures-of-merit were achieved have migrated slowly, from ~100 kS/s to 1–10 MS/s, even if state-of-the-art FOMs have occasionally been reported at several GS/s in the past. Looking at the f_s trajectory from a purely mathematical curve-fitting perspective, it would not support the trend suggested by the green curve. Weighing in some understanding of the speed-power tradeoff in actual design (described below), it makes a bit more sense. It appears thus, that the FOM is best improved by lowering the power dissipation and accepting a medium resolution, while running at moderate sampling rates.

Understanding the trajectories

In high-resolution ADCs, it can be shown that the power dissipation has a lower limit defined by the size of capacitors sized for a kT/C-noise in line with the target ENOB. The power used to drive these capacitors increase by 4X for every additional bit of resolution – in other words, as . It was shown in [3] and [4] that the break point where power dissipation becomes proportional to is currently @ 9-b ENOB for the most power efficient ADCs. It was also shown in [4] that F_A1 will always have a sweet spot at this break point.

Since F_A1 (erroneously) presupposes that P is proportional to (rather than ) for P and ENOB to be traded on equal terms, you will always improve F_A1 more by lowering P than by increasing ENOB – as long as ENOB ≥ 9. Below the 9-b break point, state-of-the-art P/f_s is approximately independent of ENOB [3]-[4],  which makes it meaningless to lower the resolution further, as it would only diminish the factor in F_A1 and do very little to reduce P/f_s. This is the reason why the trajectories has not migrated to even lower resolutions and dissipations – for example to a pathologically low ENOB with femto-Watt dissipation.

The reason state-of-the-art F_A1 values tend to be reported for 0.1–10 MS/s ADCs is perhaps less obvious. A reasonable assumption is that energy per sample (P/f_s) increase faster than linearly with f_s when sampling rates are pushed further, and therefore moderately fast designs are likely to have a more optimal P/f_s at any fixed ENOB.

Cookbook for an optimized FOM

It was shown in [2] that the state-of-the-art F_A1 also improves with every step of CMOS scaling. Including the parameter trajectories showed in this post, the recipe for a good A/D-converter FOM would be something like:

• Use the most deeply scaled CMOS process you possibly can.
• Aim for 8–9-b effective resolution, and a modest sampling rate.
• Use the lowest amount of power that will place you at the ENOB sweet spot, and let the measurements decide exactly what f_s you should claim in the paper

There are a few more tricks – some of which can be understood from [3] and some that I’ll save for clients and partners – but that’s more or less it. It will obviously help if you’re prepared to go the extra mile with your design, like the current record holders van Elzakker, et al. [6], who introduced multi-step charging of capacitors to further reduce P/f_s. Honing your design skills will help too, but essentially you’re now set to go out and design the next big scientific hit … 

Keep trying, and best wishes!

References

[1] B. E. Jonsson, “A survey of A/D-converter performance evolution,” Proc. of IEEE Int. Conf. Electronics Circ. Syst. (ICECS), Athens, Greece, pp. 768–771, Dec., 2010.

[2] B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.

[3] B. E. Jonsson, “An empirical approach to finding energy efficient ADC architectures,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011.

[4] B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011.

[5] B. E. Jonsson, “Area Efficiency of ADC Architectures,” Accepted for presentation at Eur. Conf. Circ. Theory and Des. (ECCTD), Linköping, Sweden, Aug., 2011.

[6]    M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.

ADC Survey: Spring 2011 update on FOM state-of-the-art

Experimental ADC data emerge like flowers in the spring.

Now I have finally completed the annual update of my ADC survey data. There’s a lot going on in the ADC field, so using scientific data only until March 2010 wasn’t going to be acceptable for much longer. Now the survey covers scientific ADC implementations reported all the way from 1974 until April/May 2011. Actually, I still have around 70 ADC papers from ESSCIRC 1975-1995 to read in order to make the survey backwards exhaustive, but those papers aren’t likely to change the content in this post. Therefore I’m not going to keep you waiting for this figure-of-merit status update any longer. Let’ get to the business:

Influence on state-of-the-art

With the current update, the survey data now covers 1550 unique scientific papers and we could expect some changes to the state-of-the-art registered by the ADC FOM-o-meter.

Standing Their ground

Not everything changes, though. Amazingly enough, the world record “Walden” or “ISSCC” FOM

set to 4.4 fJ by van Elzakker et al. three years ago [1] remains unchallenged. Quite impressive, indeed!

Pushing the envelope

The same SAR implementation by van Elzakker, also used to hold the state-of-the art “Thermal FOM”

for Nyquist converters, but a new record (7.6 aJ) was set by Hurrell et al. with a pipelined SAR ADC reported in December 2010 [2]. Observant blog readers may wonder why this design wasn’t already listed as state-of-the-art, since it was originally reported at ISSCC 2010. The answer is that the peak performance that nudged the state-of-the-art was measured at a very low (50 kHz), and that data point was not reported in the ISSCC paper – possibly in the slides. Since I wasn’t at the conference, any information shared in the slides was not available to me. Either way, congratulations to Christopher Peter Hurrell, and the rest of the team from Analog Devices UK and Ireland for this excellent design!

Finally, the overall best  reported by Pavan et al. [3], has been improved upon by a discrete-time DSM by Perez et al. [4] reporting a 2.7 aJ. Converter Passion is impressed by this significant contribution from Aldo Pena Perez and co-authors from University of Pavia, Italy. Congratulations!

Hall of fame

All changes are now registered on the Converter Passion ADC FOM-o-meter page – your one stop solution for monitoring the evolution of A/D-converter figures-of-merit – and you can still find the previous (and current) state-of-the-art in the newly opened Converter Passion Hall of Fame. [See the new top menu "Hall of Fame" for different halls.]

So, what do you think: Was this result to be expected, or did you find anything surprising in the update? What do you think is the best approach in order to finally beat the van Elzakker record and send it to the Hall of Fame? [Michiel and co-authors, you are obviously welcome to share your thoughts as well. Is your 4.4fJ record unbreakable?]

References

[1]    M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.

[2] C. P. Hurrell, C. Lyden, D. Laing, D. Hummerston, and M. Vickery, “An 18 b 12.5 MS/s ADC with 93 dB SNR”, IEEE J. Solid-State Circuits, Vol. 45, pp. 2647-2654, Dec., 2010.

[3]    S. Pavan, N. Krishnapura, R. Pandarinathan, and P. Sankar, “A 90μW 15-bit ΔΣ ADC for digital audio,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Munich, Germany, pp. 198–201, Sept., 2007.

[4] A. P. Perez, E. Bonizzoni, and F. Maloberti, “A 84dB SNDR 100kHz Bandwidth Low-Power Single Op-Amp Third-Order ΔΣ Modulator Consuming 140μW”, Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, USA, pp. 478-480, Feb., 2011.

Going to Italy … Yes, Yes, Yes!!

I will actually try to make some sense out of plots like this one during the IWADC.

The review results from IWADC have now reached me and, yes … it looks like I’ll be going to Orvieto this summer to present two ADC papers. It will be great fun to go. Now, the only thing that I have to do to ensure a happy stay is to prevent my wife from realizing just how beautiful the city of Orvieto and the surrounding area really are, otherwise she’ll drag me out of geek heaven (discussing data-converter issues with like-minded people in windowless conference rooms with dimmed lights) and force me to see magnificent medieval buildings, and perhaps some stunning views from the region of Umbria. Now, who would want to do that?

The two papers I’ll present are titled “An empirical approach to finding energy efficient ADC architectures” and “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance“. The first paper takes a look at the entire body of measured and scientifically published monolithic ADC implementations in order to determine the energy-efficiency of different architectures across the entire resolution range from 2 to 22 effective bits. An efficiency hierarchy of ADC architectures is extracted from the empirical data, and key low-power enablers are identified by a more specific review of the 15 most power-efficient ADCs ever reported. So, if you want to know if SAR ADCs dissipate less power than their pipeline counterparts, or what the difference is between flash and folding ADCs in terms of energy efficiency, this is a paper for you. If you come to IWADC you’ll see the scatter plots explained in real life. Trust me, you don’t want to design ultra-low-power ADCs without knowing what’s in this paper. [I could of course be biased ... ]

Believe it or not – there is some meaning to all of this too. Hopefully it will all be clear before you leave Orvieto.

The second paper reviews the practice of using figures-of-merit (FOM) to compare measured ADC performance – a topic you may recognize from this blog. In fact, the more tutorial-oriented introduction and background parts of the paper include the generic FOM and the generic FOM classes you may have seen already, while the core contribution in the paper is the analysis of FOM properties by applying them to real data. More specifically, their correlation with the two design/implementation parameters ENOB and CMOS node is observed and discussed. The entire body of measured and scientifically reported monolithic ADCs is once again used to support the analysis. Sensitive listeners should be warned about this paper – your trust in a certain FOM may be somewhat challenged during presentation

Now, didn’t that make you at least a bit curious?

And how about you? Any plans to go to IWADC 2011? Any contributions you wish to mention? Does the phrase “going to Italy” sound nice to you as well?

ADC FOM: What is a good figure-of-merit?

No rocket science: A good FOM should simply reflect the merits of the ADC

So, what is a good figure-of-merit (FOM) for analog-to-digital converters (ADC)? What is technically sound? What makes a figure-of-merit relevant, and what is good practice when using it? I’ll not able to cover everything in one post, so the plan is to keep returning to this subject over a number of posts.

What is a figure-of-merit?

So, what is a figure-o-merit in the first place, and what should we expect from a good one? Well … Wikipedia currently defines it as:

“… a quantity used to characterize the performance of a device, system or method, relative to its alternatives. In engineering, figures of merit are often defined for particular materials or devices in order to determine their relative utility for an application. In commerce, such figures are often used as a marketing tool to convince consumers to choose a particular brand.”

Another quote from the Wikipedia entry touches on the question of relevance and proper use:

“When used in deceptive advertising, the deception lies more in the question of relevance rather than truth since the number quoted as a figure of merit may not be enough to determine performance when comparing products.”

As a consumer of whatever is marketed or assessed with a FOM – be it commercial ADC parts or scientific results – I also want to know that the FOM is designed so that anything awarded a state-of-the-art value is what actually has the best performance or is more useful to me. That is a well-conceived FOM. A well-conceived FOM also gives equal value to all objects that have equivalent performance with respect to whatever the FOM is supposed to measure, while an ill-conceived FOM can give widely different values for equivalent actual merits. In short, I would say that:

A good figure-of-merit should accurately reflect the merits of the ADC in the context and for the purpose which the figure-of-merit is used.

You are welcome to share your thoughts on this. What would you expect from a good FOM? What criteria do you use to identify an ill-conceived FOM?

Purpose & context

A figure-of-merit is used for a purpose and in a context. Common purposes include:

• Marketing
• Product performance comparison
• Comparison of scientific achievement
• Identifying the best component for a particular task

The context is also important. If you want to apply a FOM to a set of commercial part specifications to find out which part is the best for your current project, then you can define pretty much any FOM expression you’d like, as long as you know it will help you detect the best circuit. The context is local – your project and your organization. You only have to convince your project team and perhaps the steering group that the FOM is technically sound and will do the job.

If, on the other hand, you wish to propose a FOM that can be universally applied to compare the merits of widely different circuits, the context is global. The demands will be higher – both with respect to the mathematical expression and your ability to convince others that the FOM is sound. We will focus on this latter case.

ADC FOM vs. CMOS node. This FOM improves with scaling.

Universal comparison of merits in a global context

Universal comparison of merits can be divided by at least two major purposes: (I) product comparison and (II) comparison of scientific achievement. When comparing the merits of a product, it doesn’t matter if a FOM is biased towards certain design parameter values. If the FOM correctly represents end user satisfaction, it is irrelevant whether or not you can always achieve a better FOM by reducing power, increasing the voltage supply, or by using a more recent manufacturing technology. If new technology makes the design easier each year, who cares? For the end user it doesn’t matter how easy or hard it was for the engineers to develop the product – as long as the FOM measures how good the product is for the user, it is all well.

When a FOM is used to measure or claim scientific achievement and progress, it does matter if certain corners of the parameter space always gives the best results. Then the FOM becomes a measure of how close you are to that corner, rather than a measure of some universal achievement. This is actually the case with the most commonly used FOM today

It was shown in [1] that a distinct feature of is that it improves with every step of CMOS scaling. Roughly improves by 100 times for every 10 times of process scaling, as seen in the FOM vs. CMOS node plot above. In practice, it means that organizations that have the possibility to use the latest technologies will always win the race with respect to , while those that refine their design in other ways (without moving to a newer technology node) have practically no chance. Its usefulness as a universal measure of scientific achievement in power-performance trade-off can therefore be questioned.

That said, it should be understood that designing in deeply scaled nanometer technologies is certainly not without challenges. Quite the contrary – it has many design challenges, and it is a scientific or engineering achievement to break new ground and design ADCs in the most recent CMOS nodes. But the point here is the particular FOM  and that process scaling almost automatically improves it. A research group that develop innovative architectures or circuit techniques that improve the power-performance trade-off within the same node is therefore much less likely to publish state-of-the-art values than a group that focus on the problems of porting its design to newer technologies. Hence , the most commonly used FOM today, heavily promotes the use of new process technology, and this should be understood when comparing the FOM reported in different papers.

I also want to clarify that I’m not suggesting that those that have defined the state-of-the-art evolution of have effortlessly surfed the wave of CMOS scaling. Many, most, or all of these designs have reached state-of-the-art through a combination of technology scaling and innovative techniques for power reduction. As an example, the design by van Elzakker et al. [2] currently listed as state-of-the-art on the FOM-o-meter page, combines the advantages of 65 nm technology with a low-energy multi-step switching charge-transfer technique to reach a truly impressive result.

Industrial and scientific relevance

As discussed above, a FOM may have relevance for comparing the performance of commercial products without being suitable for comparison of scientific achievement. In my opinion, has industrial relevance only to the extent that it measures what the buyers truly want from an ADC part. I’m not in a position to fully assess whether is representative of the market demand, or if the market has simply been taught by ADC vendors that “this is what you really want” so now the sourcing people keeps asking for it. It would certainly be interesting to hear your thoughts on that – both from a sourcing and from a vendor perspective.

Regarding scientific relevance, , a.k.a. the “ISSCC FOM” has some redeeming features in that it can be shown that an ADC with state-of-the-art is indeed highly optimized with respect to energy per sample. On the other hand, displays such a strong correlation with many design parameters, that it can also be shown that a state-of-the-art can only ever be achieved at certain sweet spots and golden corners within the design parameter space. Its almost canonical status as a global measure of scientific achievement, and possibly even criteria for publication, is therefore in my opinion questionable. Or at least something that needs a serious debate. I’m sure that many of my blog readers have an opinion too, and it would be great to hear what you think. It is no problem if you have a different view, I’d like to hear it anyway. Perhaps you can bring me back to “the narrow path” …

I hope to get back with more details on sweet spots and corners in future posts, but for now the FOM vs. CMOS node plot can serve as illustration of a “golden corner” with respect to process technology.

FOM discussions in the literature

There are only a few literature references to this post, simply because I’m not aware that any longer discussion of the topic has taken place anywhere. But if you are aware of any scientific papers, business magazine articles, application notes or web pages treating the title question of this post – “What is a good ADC FOM?” – then I’d be very happy to hear about it and to include references to them here. Please use the comment function, or email me.

Bult includes in his ESSCIRC 2009 paper [3] a brief but good discussion on how the current scientific competition is centered around , and its consequences on power dissipation reporting practices – a topic I will return to in a future post. Bult also reflects on the relevance of and in view of observed and expected correlation between ENOB and P in actual circuits. In Carsten Wulff’s Ph.D. thesis [4], there is a discussion of figures of merit, and Murmann also discusses the relevance of and briefly in his CICC 2008 paper [5].

ADC FOM DIY-kit

Now, if after reading this far you are tempted to try your hand at designing your very own and much better ADC FOM, then you have the perfect DIY-kit here at Converter Passion. It will help you to shape and define almost any FOM of your liking. You can always start building it from scratch if you feel adventurous, but why not start with the “Mother of all FOM”, and the generic FOM classes I’ve put together for you.

Enjoy, and don’t forget to share your views on ADC figures-of-merit with the rest of us.

And … if you invent a smashing ADC FOM, or already have published one that I’ve missed, be sure to post it in the comments.

Let me know if you want help getting the WordPress LaTeX to work. It can be used in the comments as well. Here’s an on-line LaTeX equation editor that makes life easier. Because the WordPress LaTeX parser is much less forgiving, the code sometimes need some final polishing before it renders correctly.

References

[1] B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.

[2] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/conversion-step 10b 1MS/s charge-redistribution ADC”, Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008, IEEE.

[3] K. Bult, “Embedded analog-to-digital converters,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Athens, Greece, pp. 52–60, Sept., 2009.

[4] Carsten Wulff, Efficient ADCs for nano-scale CMOS Technology, PhD Thesis, Norwegian University of Science and Technology, Trondheim, Norway, Dec. 2008.

[5] B. Murmann, “A/D converter trends: Power dissipation, scaling and digitally assisted architectures,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 105–112, Sept., 2008.