Converter Passion will try to plant some seeds of data converter knowledge

One of the activities I’ve planned is to list useful data converter resources on the web. First out could be recommended literature for those wanting to catch up on the basics [whatever that may be]. I’ve been contemplating making these lists for some time now, but was re-inspired by the app note/report A Glossary of Analog-to-Digital Specifications and Performance Characteristics highlighted in a recent TI newsletter. It doesn’t have to be just app notes, but it should be resources that are completely open and freely available – preferably without any registration procedures. So please e-mail me, or post a comment here with your suggestions for the best internet resources for anyone new to the field.

Being a bit old-school, I still do read books so a parallel activity will be to compile a list of good books on data conversion, data converter design & application and related topics – from entry level to the most advanced treatment. Please tell me which books you’d like to recommend, and if you feel like it you can also provide a brief review of 2–200 words describing what you like about it.

As always: Don’t be shy to promote your own work, your company or any one else you wish to give your unreserved praise. All the readers of Converter Passion are of the generous, happy type (I hope). And if you happen to have a data converter book coming out soon, let us know about it too. I’ll be more than happy to highlight it, and if you send me a copy of the final product I’ll also read it and post a book review here on the blog.

Good to see you all again …

After the crystal-clear scientific presentations at ECCTD, I'm now back in the mist again.

So, I’m back from ECCTD 2011 since late Wednesday, and up here at the southern edge of the northern half of Sweden, the mornings are misty and the leaves are turning yellow. Visiting Linköping was every bit as pleasant as I had expected. The conference was held at Linköping Konsert & Kongress, which is beautifully located at the center of the city, right next to the Linköping Cathedral.

The conference

The conference was excellently organized by the Electronics Systems division at Linköping University and the conference committee. I was particularly impressed with the student helpers. Not only were they helpful, kind and attentive, but quite a few of them also turned out to be passionate about data-converter research and development [one of the healthier states of the human mind, BTW ] and we had several interesting conversations on the topic. I couldn’t possibly have felt more welcome.

Professor Borivoje Nikolić speaks about managing variability.

After we all had been welcomed by the conference general chair, prof. Lars Wanhammar, Linköping University, the conference started with a plenary presentation “Managing Variability for Ultimate Energy Efficiency” given by prof. Borivoje Nikolić from UC Berkeley, USA. The conference then split up into various sessions which are described in detail in the program. ECCTD is a rather broad conference, but there were at least three dedicated data-converter sessions: “Sigma-Delta Modulators“, “Data Converters“, and “Pipelined ADCs“. I had the honor of chairing “Pipelined ADCs“, and I presented my own contribution “Area Efficiency of ADC Architectures” in the “Data Converters” session. I might come back to the content of that paper in another post, but in short (for those of you that were not there), it surveys the chip area vs. performance in speed and resolution for just about every ADC implementation reported in the scientific literature all the way since 1974 – approximately 1500 papers. A normalized area measure

was proposed based on the observed correlation between absolute chip area (A) and effective resolution (ENOB). State-of-the-art A_Q – a.k.a. “Area per effective quantization step” – was seen to be independent not only of ENOB, but also of sampling rate over a broad range of sampling rates and resolutions, respectively. It is also approximately independent of CMOS process node. Chip area per effective quantization step was then compared for individual architectures, and design guidelines derived for area-optimal ADC architecture selection at any given speed and resolution specification. It was seen that there are large differences in the peak area efficiency achieved with different ADC architectures. There is for example a factor of 3 difference between SAR and pipeline, and a factor of 10 between pipeline and flash. Such big area differences can translate to a lot of money if you’re developing high-volume ADCs. So make sure you get hold of this paper as soon as it comes up on IEEE Xplore.

The blogger as session chair. Photo: Mark Vesterbacka

Professor Mark Vesterbacka, Linköping University had to push the electronics in his mobile phone to the maximum in order to document my chairing efforts in spite of the low light. Thanks for sending the picture.

CWCP winner

I could notice a slight peak in blog visitors yesterday. I assume that many of you wanted to know who won the Connect-with-Converter Passion (CWCP) prize, and I apologize for not being as fast as Dr. J Jacob Wikner who was blogging live from ECCTD and managed to fire away several conference-related post on Mixed-Signal Electronics while ECCTD was still developing. One of them correctly revealing that we had a CWCP winner already after the first day. And the winner is:

CWCP-winner Kiran Kariyannawar

Kiran Kariyannawar from Ericsson AB, who showed the enthusiasm and dedication necessary to win the CWCP prize for ECCTD. Congratulations Kiran! Kiran was there together with other Ericsson colleagues to demonstrate The Connected Tree and how to transmit audio and video signals through the human body. Quite far out compared to most demonstrations I’ve seen at scientific conferences. Very fun (at lest from a tech nerd’s perspective), and I’m sure they will figure out a lot of applications for it eventually, although for now they didn’t seem quite sure what to do with it. At least not with the connected tree. I played a bit with the human-body transmission (by becoming the channel), and I think it could be great for DJ-ing. I was just about to get it to rock big time when I started to realize the other delegates need for less noise and gave it up. If only I had a few more minutes to work out that groove …

The next big thing in DJ-ing? Just intermittently add a human body connected between those metal plates – preferably in a rhythmic pattern – and you're all set.

Other impressions

The conference dinner was held at the Air Force Museum – a place I’m likely to return to again to have more time to look at everything. Most likely with the rest of the family. A few photos below will give you some idea of the location. Finding unorthodox locations that can make the conference dinner extra memorable is probably a real challenge to most organizers. Unless they start taking us to outer space and back, I believe that the abundant food stations in combination with the breathtaking beauty of sea life shown at Monterey Bay Aquarium (ISCAS 1998) will remain my personal favorite for the rest of my life, but with ECCTD 2011 now being among the top two. Excellent work!

A classic Swedish beauty.

Chopper techniques. Large implementation.

A peaceful dinner ...

A missile of some kind, with a sign in Swedish saying "DO NOT PUSH HERE". Now, how irresistible is that on a scale to ten? Photo: M. Reza Sadeghifar

Having been to a few conferences, you start to recognize some faces that keep coming back. I had the pleasure of meeting delegates I’ve recently met. Some at NORCHIP, some at ICECS, and others at IWADC. It was great seeing you all. That is the real value of going to conferences.

Peace! 

ECCTD 2011 face-recognition. Note that we observed a severe Linköping bias here that might be compensated for in "future work".

Same face – new conference

To win the prize (which is the glory of winning + some visibility on this blog), all you need to do is to be the first one to locate me during the conference and claim the prize. Couldn’t be much simpler. Since the Linköping University group that is organizing the conference has a strong history of winning the CWCP prize, I will discriminate slightly against them this time (sorry guys) – but just slightly – to give the rest of you a fair chance. Affiliates of Linköping University will not be allowed to claim the prize until the second day of the conference (Tuesday). But don’t forget to try, because it may still be up for grabs by then.

If you haven’t located me before that, Tuesday is also a safe day to find me, as I’m presenting my ECCTD contribution “Area Efficiency of ADC Architectures” in session T21, Data Converters (starting 15:50). Last chance is around the W33 session, Pipelined ADCs, which I’ll be chairing on Wednesday afternoon.

Looking forward to seeing you in Linköping next week.

Figure 1. ENOB, power, and sampling rate trajectories showing the evolution path to the current state-of-the art FOM.

If you are participating in the scientific competition to report an ever better ADC figure-of-merit (FOM), you will find some pretty useful information in this post. Basically it will tell you where to start “drilling for oil”, and with a bit of persistence (preferably combined with some skill in the art) it might take you all the way to ISSCC 2013. The deadline for ISSCC 2012 is probably a bit too close for anyone to make a full ADC implementation according to these guidelines and still get it back in time from the foundry. But you can always try. I will give you a set of information about design and performance parameters that will enable you to predict quite accurately where in the design space the next state-of-the-art ADC (with respect to FOM) will be located. Remember that it could be your ADC, if you choose to optimize the speed-resolution-power tradeoff for this particular target.

First, let us clarify that we are talking about the most commonly used ADC figure-of-merit of all:

Figure 1 illustrates the trajectories of each of the three parameters in F_A1 as F_A1 improved over time. Click on the image to enlarge it. Only the data points representing an advance of F_A1 state-of-the-art, i.e., the monotonic decrease of F_A1 over time are used in the plot. Time was also quantized so that only the single best ADC per year appears in the trajectories. The underlying data set is gathered from 1600 scientific papers, and the same as used in [1]-[5]. The FOM axis and the FOM values for each dot are the same for all three plots, while the x axes show the simultaneous values of ENOB, power dissipation and sampling rate, respectively. These are the three parameters used to calculate the FOM, so any systematic trends in their trajectories are likely to be a good direction for a FOM-optimized design.

Figure 2. Approximate trajectory trends suggested by the plots.

Although there is plenty of noise in some of the trajectories, visual inspection suggests the approximate trends indicated in Fig. 2. At least it is my best guesstimate. It is purely ad hoc, and you are of course invited to discuss and refine my estimates by posting comments below. The most obvious trend applies to power dissipation (P), which has reduced by almost six orders of magnitude – from Watts to micro-Watts. At the same time the effective resolution (ENOB) has followed a more noisy, but visible path towards lower (medium) resolutions – from ~14 to currently 9-b ENOB. The change equals a three orders of magnitude increase in error power. Finally, the sampling rates at which state-of-the-art figures-of-merit were achieved have migrated slowly, from ~100 kS/s to 1–10 MS/s, even if state-of-the-art FOMs have occasionally been reported at several GS/s in the past. Looking at the f_s trajectory from a purely mathematical curve-fitting perspective, it would not support the trend suggested by the green curve. Weighing in some understanding of the speed-power tradeoff in actual design (described below), it makes a bit more sense. It appears thus, that the FOM is best improved by lowering the power dissipation and accepting a medium resolution, while running at moderate sampling rates.

Understanding the trajectories

In high-resolution ADCs, it can be shown that the power dissipation has a lower limit defined by the size of capacitors sized for a kT/C-noise in line with the target ENOB. The power used to drive these capacitors increase by 4X for every additional bit of resolution – in other words, as . It was shown in [3] and [4] that the break point where power dissipation becomes proportional to is currently @ 9-b ENOB for the most power efficient ADCs. It was also shown in [4] that F_A1 will always have a sweet spot at this break point.

Since F_A1 (erroneously) presupposes that P is proportional to (rather than ) for P and ENOB to be traded on equal terms, you will always improve F_A1 more by lowering P than by increasing ENOB – as long as ENOB ≥ 9. Below the 9-b break point, state-of-the-art P/f_s is approximately independent of ENOB [3]-[4],  which makes it meaningless to lower the resolution further, as it would only diminish the factor in F_A1 and do very little to reduce P/f_s. This is the reason why the trajectories has not migrated to even lower resolutions and dissipations – for example to a pathologically low ENOB with femto-Watt dissipation.

The reason state-of-the-art F_A1 values tend to be reported for 0.1–10 MS/s ADCs is perhaps less obvious. A reasonable assumption is that energy per sample (P/f_s) increase faster than linearly with f_s when sampling rates are pushed further, and therefore moderately fast designs are likely to have a more optimal P/f_s at any fixed ENOB.

Cookbook for an optimized FOM

It was shown in [2] that the state-of-the-art F_A1 also improves with every step of CMOS scaling. Including the parameter trajectories showed in this post, the recipe for a good A/D-converter FOM would be something like:

• Use the most deeply scaled CMOS process you possibly can.
• Aim for 8–9-b effective resolution, and a modest sampling rate.
• Use the lowest amount of power that will place you at the ENOB sweet spot, and let the measurements decide exactly what f_s you should claim in the paper

There are a few more tricks – some of which can be understood from [3] and some that I’ll save for clients and partners – but that’s more or less it. It will obviously help if you’re prepared to go the extra mile with your design, like the current record holders van Elzakker, et al. [6], who introduced multi-step charging of capacitors to further reduce P/f_s. Honing your design skills will help too, but essentially you’re now set to go out and design the next big scientific hit … 

Keep trying, and best wishes!

References

[1] B. E. Jonsson, “A survey of A/D-converter performance evolution,” Proc. of IEEE Int. Conf. Electronics Circ. Syst. (ICECS), Athens, Greece, pp. 768–771, Dec., 2010.

[2] B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.

[3] B. E. Jonsson, “An empirical approach to finding energy efficient ADC architectures,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011.

[4] B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011.

[5] B. E. Jonsson, “Area Efficiency of ADC Architectures,” Accepted for presentation at Eur. Conf. Circ. Theory and Des. (ECCTD), Linköping, Sweden, Aug., 2011.

[6]    M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.

I’ve been contemplating the fact that authors may spend 9-12 months (or 1–1.5% of their lifetime) conceiving, modeling, designing and measuring their ADCs, but when they finally write their papers, some choose to make as little impact as possible by omitting nearly everything that could be of interest to the scientific and engineering community. Imagine yourself spending 1-1.5% of your life earnings on something (that’s like 5 to 7 months salary). Then you’d want it to make a difference, right? So, why not in (some) papers?

I can understand that companies may want to hide some information to avoid helping competitors, and I do understand that academic competition can sometimes be just as fierce. But if neither corporations nor universities feel they can openly report their results, where does that leave our field? Do we really want a “science” where everybody is competing to be the first to come up with something of which they tell nothing?

If not, what can be done about it, and what parameters do you expect to see in a good ADC paper?

Curves like these can be really useful if you're going for small chip area. Those who attend ECCTD 2011 will get the full picture and learn what's on the X and Y axes.

You’d be forgiven to think that, with all the praise I recently gave to Italy and the IWADC conference, there’s no room in my heart for any other conference or location. But going to the European Conference on Circuit Theory and Design in Linköping, Sweden will be very special. The location isn’t nearly as exotic to me as Italy – quite the opposite in fact. I used to study in Linköping, and I was also a PhD student at the very department that is hosting the conference. What is special with Linköping is that it’s the city I used to call home for about 15 years of my life – 15 good years filled with memorable moments, good friends and talented engineers and scientists. It’s a nice Swedish town, and I highly recommend you to go there. ECCTD 2011 offers the perfect excuse.

If, like me, you’re also interested in what’s actually presented at the conference, it too is an excellent reason to go there. I guess there will be a conference program up on the conference site sooner or later. Until then I can only tell you about my contribution “Area Efficiency of ADC Architectures”, which I was very glad to get accepted. No extra points for guessing the general topic of the paper, and I’m not going to spoil the fun by telling you everything about it. Suffice to say that it’s another huge survey of scientific A/D-converter achievements. This time we’ll take a first look at the area-efficiency of various ADC architectures at different speed/resolution specifications. It exemplifies a small fraction of the EDO methodology used by ADMS Design AB, and gives you some overall guidelines to get you started with area-optimized ADC design.

So, if you design ADCs for high volume production and a low manufacturing cost is important … don’t miss this paper.

Stuff like this makes a tech-blogging nerd happy ...

A very pleasant recent observation is that this blogs scientific citation frequency just improved by ∞ % (from zero to one), thanks to an IWADC paper [1] referring to a Converter Passion post [2]. It may be a humble start, but it was good news to see that someone out there trusts the data on this blog enough to include it as a reference in a scientific publication. To the best of my knowledge that was a first for Converter Passion, but let me know if you get a paper published that cites Converter Passion. Should it become a trend, I might have to compile a list of citations here, but I’ll wait until we have at least two …

References

[1]    F. Fuiano, L. Cagnazzo, and P. Carbone, “Data Converters: an Empirical Research on the Correlation between Scientific Literature and Patenting Activity,” Proc. of Int. Workshop on ADC Modelling, Testing and Data Converter Analysis and Design (IWADC), Orvieto, Italy, June, 2011.

[2] B. E. Jonsson, “Who has done all that A/D-converter research?,” Converter Passion, Nov. 6, 2010, Available: http://converterpassion.wordpress.com

Views from Orvieto (click to enlarge)

I’m completely in love with Italy now. It was my first time there, and I was impressed by just about every aspect of the visit – the beautiful landscape, the fascinating history embodied in ancient buildings, and of course by the people. Perhaps it was accentuated by me going through the “vanilla phase” with Italy, but it did seem very easy to get a kind smile from just about any Italian I met throughout the entire trip.

A fraction of the big happy family of IWADC delegates

Attending IWADC 2011 was every bit as pleasant: The conference itself ran like clockwork, the medieval city of Orvieto was a decidedly pretty conference location, and the relatively small size of the conference contributed to the relaxed and friendly character of the event. Almost like a family event – a big happy Italian family, I could imagine . The feeling of being welcome and surrounded by “family” was very much accentuated by the hospitality shown by the conference general chair, professor Paolo Carbone (University of Perugia), members of the organizing committee, and other delegates. During the conference dinner when we were also treated with one tasty Italian dish after another, I remember uttering something like “all conferences should be in Italy”. That’s how good it felt to be there.

Who doesn't love Italian food? I was late to some sessions because I tried to eat all the Salatini before they cleared the tables ...

CWCP winner

A winner: Yu Lin

Now being a solid tradition, each conference I attend needs to have an opportunity to connect with Converter Passion. To motivate conference delegates to not be shy we came up with the Connect with Converter Passion (CWCP) prize. The rules are simple: First blog reader to find me at the conference and claim the prize is the winner, and for IWADC 2011 the winner is Yu Lin, a PhD student at Technical University of Eindhoven who was also presenting the paper “An Input Signal Statistics Aware Design Approach and Examples for Analog-to-Digital Converters for communication systems” at the conference [co-authors: Kostas Doris (NXP), Hans Hegt and Arthur van Roermund (TU Eindhoven)]. It was a pleasure to meet such a motivated blog reader. Yu aimed for victory and did not hesitate to claim the prize already at the informal pre-conference reception at restaurant Maurizio. Definitely the right spirit and a worthy winner indeed. Congratulations! Normally, the competition is only for the glory, but this time a small surprise memento was added in the form of a handmade key ring in black leather produced by “Boothill Bob” from Boothill Bob Holsters.

The conference

IWADC covers ADC modeling, testing and data converter analysis and design. Because it is an IMEKO conference, various aspects of measurement becomes a natural thread in many contributions, although the scope is rather wide. It includes calibration of ADCs and error correction of the ADC output, such as presented in the papers “Digital background calibration of subsampling time-interleaved ADCs” by Centurelli from Università di Roma la Sapienza, and “A Linearization Strategy for Undersampling Analog-to-Digital Converters” by Vallant from Cassidian Electronics. Time-to-Digital Converters (TDC) seems to be a growing field, and a fair number of papers addressed various aspects of TDCs, for example “Modeling Noise Effects in Time-to-Digital Converters” by Napolitano, University of Perugia, and “Time-to-Digital Converter (TDC) with Sub-ps-Level Resolution using Current DAC and Digitally Controllable Load Capacitor ” by Alahdab from University of Oulu. There were classic ADC implementation papers such as “A 6-bit 3GS/s Flash ADC in Bipolar 0.25 um for the radiotelescope SKA” by Da Silva from Station de Radioastronomie de Nançay, and I personally found it interesting to hear about ADC implementations in emerging materials, as in “ADC Design in Organic Thin-Film Electronics Technology on Plastic Foil” by Marien of K. U. Leuven.

Scientific discussions

Of my own contributions, the first (An empirical approach to finding energy efficient ADC architectures) was about using the measured performance of chips made by others to better optimize your own design, and the second (Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance) treated how to assess the quality of figures-of-merit often used to make comparisons of measured performance.

IWADC face recognition

There were many more papers presented at the conference, but I don’t intend to walk you through the entire program. Note also that I have mostly mentioned the first authors above although most papers have one or more co-authors. Please add comments below and tell us about any papers, co-authors or delegates that you wish to mention. Or just say hi, and let everybody know you were there too. Share the name of your contribution, and your impressions from the conference with us.

Yes, I was there. Here together with publication chair, Dr. Antonio Moschitta (left) and general chair, professor Paolo Carbone (right).

To round it off, I’ve made a pie chart of the distribution of delegates between countries, based on statistics provided by professor Carbone. As could be expected, the Italian representation was strong. The rest of the countries are quite evenly represented. As you can see, delegates came from both USA and China, although the vast majority were from European countries.

Distribution of IWADC 2011 delegates by country

Please post your comments below if there is anything you’d like to add about the conference.

Look for this face

If you haven’t found me before, a safe bet is around the High-efficiency Data Converters session (Thursday 14:15–15:45) where I will present my first contribution An empirical approach to finding energy efficient ADC architectures , or at the Poster Session II for which I am chair on Friday, and where I will also present my second contribution Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance. For more details, see the “Going to Italy, Yes, Yes, Yes!” post, and the conference program.

Figure 1. ADC research origin (first author). Absolute amount of papers.

Figure 2. ADC research origin (first author). Relative amount of papers.

Is A/D-converter research becoming a purely academic exercise? Well, looking at the statistics for scientific ADC implementation papers shown in the two graphs above, that certainly seems to be the future for open A/D-converter research. What are the implications, and does it matter?

Figure 1 shows the number of published ADC papers over time, separated into type of origin, as determined by the affiliation of the first author {Academic, Institute, Industry}. Although a simplification, it is believed to be a fairly accurate indication of where most of the work was done. The term Institute is referring to entities that are neither universities nor traditional companies, i.e., organizations like IMEC. Figure 2 shows the relative amount of contributions from each sector, based on the same data.

Where is corporate ADC research going?

Figure 2 paints a very clear picture: The industrial “market share” of scientific  publications has had a noisy but linear negative trend almost from the start. If the trend holds – and there are actually no signs in the graph that it won’t – there will be no scientific ADC papers from industry published after year 2020–2025! At least not with the first author being from the industry.

I find that quite remarkable and slightly counter-intuitive. Aren’t academic scientists the first to explore the un-explored, and after having spent a lot of time weeding out the less fruitful approaches, they finally come up with something that works? After which the industry wakes up and jumps on the bandwagon? The ADC field appears to do exactly the reverse: After initially been doing 100% of the work, the industry is now gradually letting the universities take over the field.

We are talking about the open research literature here, so it doesn’t necessarily mean that there is no activity within the companies. It just isn’t getting out. So, what do you think:

• Does the industry feel that there is nothing more to improve or research? If so, why can academic papers still get published?
• Is the industry increasingly putting a lid on their research to survive the competition?
• Or is it just a better business to focus on shifting parts, while letting universities innovate and then pick new solutions as they get published?