ADC Survey: Spring 2012 update on FOM state-of-the-art

Will reading tons of ADC papers grow your brain — or wear it out?

Well folks, its the time of year when an A/D-converter survey update is due. Since a significant effort is still invested in the quest for ever-improving figures-of-merit (FOM), I’ll start by firing up the Converter Passion FOM-o-meter  and apply it to the body of ADC science. The latter is here approximated by my pet project – the ADC performance survey.

Including the papers added since last year, the updated survey now has 3628 experimental data points extracted from 1708 scientific papers published between 1974 and April/May 2012. The number of unique ADC implementations will be slightly less, since some papers are full-length versions of conference contributions. The source publications monitored are listed here.

What a difference a year makes …

… or not?

ISSCC/Walden-FOM

Can you believe this: With all the current competition to get a great ISSCC/Walden-FOM

the state-of-the-art (4.4 fJ) reported by van Elzakker et al. at ISSCC four years ago [1] is still number one. Their design really went the extra mile with respect to getting a low energy per sample, and I guess that paid off big time. Well done!

As Michiel commented, it is just a matter of time before someone goes below 4.4 fJ. This is also reflected in the scientific output over the last twelve months. Although the current world record didn’t change, there are several designs that reported an < 10 fJ, and that’s not bad either. They are:

FOM [fJ]	Speed [S/s]	ENOB	Architecture	1st Author	Ref
8.7	2M	8.27	SAR	Sekimoto	[2]
6.8	1k	8.52	SAR	Lu	[3]
6.5	4M	9.4	SAR	Harpe	[4]
6.1	1.1M	7.48	SAR	Shikata	[5]
6.8	10M	10.0	SAR	Verbruggen	[6]
9.7	250M	9.45	SAR	Verbruggen	[6]

The most striking feature is probably that they are all SAR ADCs. Secondly, while they are all impressive efforts, the one that stands out a bit is the design by Verbruggen et al. It maintains a sub-10fJ FOM at a significantly higher sampling rate (250 MS/s) while also reporting the highest resolution [6].

Although it’s beyond the scope of this post, it can be good to keep in mind that there are other aspects to factor in than simply the FOM value when analyzing energy efficiency. It was pointed out by Verbruggen [6] that previous ultra-low FOM ADCs have been reported only at rather low sampling rates or moderate resolution. It is a greater challenge to maintain a low for high sampling rates. Hence, pragmatic limits to the state-of-the-art are speed-dependent. It has also been shown that the limits are both scaling- and resolution-dependent [7, 8], so a perfectly fair comparison between designs is difficult to make. I can pretty much guarantee that I’ll get back to this topic in the future, but for the remainder of this post we’ll just look at the raw FOM numbers as they are.

Thermal FOM

It would have been boring to read another 100+ papers and still have nothing new to report, so I’m very glad to see that the so called “Thermal FOM”

has been improved by over a factor of two through the switched-opamp (SO) based ∆∑ design reported by Xu et al. [9]. Previous state-of-the-art – 2.7aJ reported by Perez et al. [10] – will assume its well-earned place in the Hall of Fame, while we applaud the 1.1 aJ achieved by the Chinese team from Zheijan University and Analog Devices, Shanghai. You’re the best now. Enjoy!

Thermal FOM for Nyquist ADCs

There has also been some evolution among the Nyquist ADCs: The 250MS/s SAR ADC by Verbruggen et al. mentioned above, is actually the new Thermal-FOM champion for Nyquist ADCs as it nudges the previous record [11] from 7.6 to 6.6 aJ. The authors are with imec, Belgium, and Renesas Electronics, Japan. Congratulations!

Old and new winners are always found in the halls of fame for Thermal and Walden FOM, respectively. If you are only interested in checking for the current leaders, the FOM-o-meter gives you both with a single click.

As always: I do believe the information here is correct, but if I’ve misrepresented anyone or forgotten to mention someone that should have been included, just send me an email or post a comment below.

References

[1] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.

[2] R. Sekimoto, A. Shikata, T. Kuroda, and H. Ishikuro, “A 40nm 50S/s – 8MS/s Ultra Low Voltage SAR ADC with Timing Optimized Asynchronous Clock Generator,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Helsinki, Finland, pp. 471–474, Sept., 2011.

[3] T.-C. Lu, L.-D. Van, C.-S. Lin, C.-M. Huang, “A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/Conversion-Step SAR ADC for Biomedical Applications,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.

[4] P. Harpe, Y. Zhang, G. Dolmans, K. Philips, and H. De Groot, “A 7-to-10b 0-to-4MS/s Flexible SAR ADC with 6.5-to-16fJ/conversion-step,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 472–473, Feb., 2012.

[5] A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS,” IEEE J. Solid-State Circuits, Vol. 47, pp. 1022–1030, Apr., 2012.

[6] B. Verbruggen, M. Iriguchi, and J. Craninckx, “A 1.7mW 11b 250MS/s 2× Interleaved Fully Dynamic Pipelined SAR ADC in 40nm Digital CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 466–467, Feb., 2012.

[7] B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.

[8] B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, June 2011.

[9] J. Xu, X. Wu, M. Zhao, R. Fan, H. Wang, X. Ma, and B. Liu, “Ultra Low-FOM High-Precision ΔΣ Modulators with Fully-Clocked SO and Zero Static Power Quantizers,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.

[10] A. P. Perez, E. Bonizzoni, and F. Maloberti, “A 84dB SNDR 100kHz Bandwidth Low-Power Single Op-Amp Third-Order ΔΣ Modulator Consuming 140μW,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, USA, pp. 478-480, Feb., 2011.

[11] C. P. Hurrell, C. Lyden, D. Laing, D. Hummerston, and M. Vickery, “An 18 b 12.5 MS/s ADC With 93 dB SNR,” IEEE J. Solid-State Circuits, Vol. 45, pp. 2647-2654, Dec., 2010.

The path to a good A/D-converter FOM

Figure 1. ENOB, power, and sampling rate trajectories showing the evolution path to the current state-of-the art FOM.

If you are participating in the scientific competition to report an ever better ADC figure-of-merit (FOM), you will find some pretty useful information in this post. Basically it will tell you where to start “drilling for oil”, and with a bit of persistence (preferably combined with some skill in the art) it might take you all the way to ISSCC 2013. The deadline for ISSCC 2012 is probably a bit too close for anyone to make a full ADC implementation according to these guidelines and still get it back in time from the foundry. But you can always try. I will give you a set of information about design and performance parameters that will enable you to predict quite accurately where in the design space the next state-of-the-art ADC (with respect to FOM) will be located. Remember that it could be your ADC, if you choose to optimize the speed-resolution-power tradeoff for this particular target.

First, let us clarify that we are talking about the most commonly used ADC figure-of-merit of all:

Figure 1 illustrates the trajectories of each of the three parameters in F_A1 as F_A1 improved over time. Click on the image to enlarge it. Only the data points representing an advance of F_A1 state-of-the-art, i.e., the monotonic decrease of F_A1 over time are used in the plot. Time was also quantized so that only the single best ADC per year appears in the trajectories. The underlying data set is gathered from 1600 scientific papers, and the same as used in [1]-[5]. The FOM axis and the FOM values for each dot are the same for all three plots, while the x axes show the simultaneous values of ENOB, power dissipation and sampling rate, respectively. These are the three parameters used to calculate the FOM, so any systematic trends in their trajectories are likely to be a good direction for a FOM-optimized design.

Figure 2. Approximate trajectory trends suggested by the plots.

Although there is plenty of noise in some of the trajectories, visual inspection suggests the approximate trends indicated in Fig. 2. At least it is my best guesstimate. It is purely ad hoc, and you are of course invited to discuss and refine my estimates by posting comments below. The most obvious trend applies to power dissipation (P), which has reduced by almost six orders of magnitude – from Watts to micro-Watts. At the same time the effective resolution (ENOB) has followed a more noisy, but visible path towards lower (medium) resolutions – from ~14 to currently 9-b ENOB. The change equals a three orders of magnitude increase in error power. Finally, the sampling rates at which state-of-the-art figures-of-merit were achieved have migrated slowly, from ~100 kS/s to 1–10 MS/s, even if state-of-the-art FOMs have occasionally been reported at several GS/s in the past. Looking at the f_s trajectory from a purely mathematical curve-fitting perspective, it would not support the trend suggested by the green curve. Weighing in some understanding of the speed-power tradeoff in actual design (described below), it makes a bit more sense. It appears thus, that the FOM is best improved by lowering the power dissipation and accepting a medium resolution, while running at moderate sampling rates.

Understanding the trajectories

In high-resolution ADCs, it can be shown that the power dissipation has a lower limit defined by the size of capacitors sized for a kT/C-noise in line with the target ENOB. The power used to drive these capacitors increase by 4X for every additional bit of resolution – in other words, as . It was shown in [3] and [4] that the break point where power dissipation becomes proportional to is currently @ 9-b ENOB for the most power efficient ADCs. It was also shown in [4] that F_A1 will always have a sweet spot at this break point.

Since F_A1 (erroneously) presupposes that P is proportional to (rather than ) for P and ENOB to be traded on equal terms, you will always improve F_A1 more by lowering P than by increasing ENOB – as long as ENOB ≥ 9. Below the 9-b break point, state-of-the-art P/f_s is approximately independent of ENOB [3]-[4],  which makes it meaningless to lower the resolution further, as it would only diminish the factor in F_A1 and do very little to reduce P/f_s. This is the reason why the trajectories has not migrated to even lower resolutions and dissipations – for example to a pathologically low ENOB with femto-Watt dissipation.

The reason state-of-the-art F_A1 values tend to be reported for 0.1–10 MS/s ADCs is perhaps less obvious. A reasonable assumption is that energy per sample (P/f_s) increase faster than linearly with f_s when sampling rates are pushed further, and therefore moderately fast designs are likely to have a more optimal P/f_s at any fixed ENOB.

Cookbook for an optimized FOM

It was shown in [2] that the state-of-the-art F_A1 also improves with every step of CMOS scaling. Including the parameter trajectories showed in this post, the recipe for a good A/D-converter FOM would be something like:

• Use the most deeply scaled CMOS process you possibly can.
• Aim for 8–9-b effective resolution, and a modest sampling rate.
• Use the lowest amount of power that will place you at the ENOB sweet spot, and let the measurements decide exactly what f_s you should claim in the paper

There are a few more tricks – some of which can be understood from [3] and some that I’ll save for clients and partners – but that’s more or less it. It will obviously help if you’re prepared to go the extra mile with your design, like the current record holders van Elzakker, et al. [6], who introduced multi-step charging of capacitors to further reduce P/f_s. Honing your design skills will help too, but essentially you’re now set to go out and design the next big scientific hit … 

Keep trying, and best wishes!

References

[1] B. E. Jonsson, “A survey of A/D-converter performance evolution,” Proc. of IEEE Int. Conf. Electronics Circ. Syst. (ICECS), Athens, Greece, pp. 768–771, Dec., 2010.

[2] B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.

[3] B. E. Jonsson, “An empirical approach to finding energy efficient ADC architectures,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011.

[4] B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011.

[5] B. E. Jonsson, “Area Efficiency of ADC Architectures,” Accepted for presentation at Eur. Conf. Circ. Theory and Des. (ECCTD), Linköping, Sweden, Aug., 2011.

[6]    M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.

Going to Linköping … Yes, Yes, Yes!!

Curves like these can be really useful if you're going for small chip area. Those who attend ECCTD 2011 will get the full picture and learn what's on the X and Y axes.

You’d be forgiven to think that, with all the praise I recently gave to Italy and the IWADC conference, there’s no room in my heart for any other conference or location. But going to the European Conference on Circuit Theory and Design in Linköping, Sweden will be very special. The location isn’t nearly as exotic to me as Italy – quite the opposite in fact. I used to study in Linköping, and I was also a PhD student at the very department that is hosting the conference. What is special with Linköping is that it’s the city I used to call home for about 15 years of my life – 15 good years filled with memorable moments, good friends and talented engineers and scientists. It’s a nice Swedish town, and I highly recommend you to go there. ECCTD 2011 offers the perfect excuse.

If, like me, you’re also interested in what’s actually presented at the conference, it too is an excellent reason to go there. I guess there will be a conference program up on the conference site sooner or later. Until then I can only tell you about my contribution “Area Efficiency of ADC Architectures”, which I was very glad to get accepted. No extra points for guessing the general topic of the paper, and I’m not going to spoil the fun by telling you everything about it. Suffice to say that it’s another huge survey of scientific A/D-converter achievements. This time we’ll take a first look at the area-efficiency of various ADC architectures at different speed/resolution specifications. It exemplifies a small fraction of the EDO methodology used by ADMS Design AB, and gives you some overall guidelines to get you started with area-optimized ADC design.

So, if you design ADCs for high volume production and a low manufacturing cost is important … don’t miss this paper.

Back from IWADC 2011

Views from Orvieto (click to enlarge)

I’m completely in love with Italy now. It was my first time there, and I was impressed by just about every aspect of the visit – the beautiful landscape, the fascinating history embodied in ancient buildings, and of course by the people. Perhaps it was accentuated by me going through the “vanilla phase” with Italy, but it did seem very easy to get a kind smile from just about any Italian I met throughout the entire trip.

A fraction of the big happy family of IWADC delegates

Attending IWADC 2011 was every bit as pleasant: The conference itself ran like clockwork, the medieval city of Orvieto was a decidedly pretty conference location, and the relatively small size of the conference contributed to the relaxed and friendly character of the event. Almost like a family event – a big happy Italian family, I could imagine . The feeling of being welcome and surrounded by “family” was very much accentuated by the hospitality shown by the conference general chair, professor Paolo Carbone (University of Perugia), members of the organizing committee, and other delegates. During the conference dinner when we were also treated with one tasty Italian dish after another, I remember uttering something like “all conferences should be in Italy”. That’s how good it felt to be there.

Who doesn't love Italian food? I was late to some sessions because I tried to eat all the Salatini before they cleared the tables ...

CWCP winner

A winner: Yu Lin

Now being a solid tradition, each conference I attend needs to have an opportunity to connect with Converter Passion. To motivate conference delegates to not be shy we came up with the Connect with Converter Passion (CWCP) prize. The rules are simple: First blog reader to find me at the conference and claim the prize is the winner, and for IWADC 2011 the winner is Yu Lin, a PhD student at Technical University of Eindhoven who was also presenting the paper “An Input Signal Statistics Aware Design Approach and Examples for Analog-to-Digital Converters for communication systems” at the conference [co-authors: Kostas Doris (NXP), Hans Hegt and Arthur van Roermund (TU Eindhoven)]. It was a pleasure to meet such a motivated blog reader. Yu aimed for victory and did not hesitate to claim the prize already at the informal pre-conference reception at restaurant Maurizio. Definitely the right spirit and a worthy winner indeed. Congratulations! Normally, the competition is only for the glory, but this time a small surprise memento was added in the form of a handmade key ring in black leather produced by “Boothill Bob” from Boothill Bob Holsters.

The conference

IWADC covers ADC modeling, testing and data converter analysis and design. Because it is an IMEKO conference, various aspects of measurement becomes a natural thread in many contributions, although the scope is rather wide. It includes calibration of ADCs and error correction of the ADC output, such as presented in the papers “Digital background calibration of subsampling time-interleaved ADCs” by Centurelli from Università di Roma la Sapienza, and “A Linearization Strategy for Undersampling Analog-to-Digital Converters” by Vallant from Cassidian Electronics. Time-to-Digital Converters (TDC) seems to be a growing field, and a fair number of papers addressed various aspects of TDCs, for example “Modeling Noise Effects in Time-to-Digital Converters” by Napolitano, University of Perugia, and “Time-to-Digital Converter (TDC) with Sub-ps-Level Resolution using Current DAC and Digitally Controllable Load Capacitor ” by Alahdab from University of Oulu. There were classic ADC implementation papers such as “A 6-bit 3GS/s Flash ADC in Bipolar 0.25 um for the radiotelescope SKA” by Da Silva from Station de Radioastronomie de Nançay, and I personally found it interesting to hear about ADC implementations in emerging materials, as in “ADC Design in Organic Thin-Film Electronics Technology on Plastic Foil” by Marien of K. U. Leuven.

Scientific discussions

Of my own contributions, the first (An empirical approach to finding energy efficient ADC architectures) was about using the measured performance of chips made by others to better optimize your own design, and the second (Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance) treated how to assess the quality of figures-of-merit often used to make comparisons of measured performance.

IWADC face recognition

There were many more papers presented at the conference, but I don’t intend to walk you through the entire program. Note also that I have mostly mentioned the first authors above although most papers have one or more co-authors. Please add comments below and tell us about any papers, co-authors or delegates that you wish to mention. Or just say hi, and let everybody know you were there too. Share the name of your contribution, and your impressions from the conference with us.

Yes, I was there. Here together with publication chair, Dr. Antonio Moschitta (left) and general chair, professor Paolo Carbone (right).

To round it off, I’ve made a pie chart of the distribution of delegates between countries, based on statistics provided by professor Carbone. As could be expected, the Italian representation was strong. The rest of the countries are quite evenly represented. As you can see, delegates came from both USA and China, although the vast majority were from European countries.

Distribution of IWADC 2011 delegates by country

Please post your comments below if there is anything you’d like to add about the conference.

ADC Survey: Spring 2011 update on FOM state-of-the-art

Experimental ADC data emerge like flowers in the spring.

Now I have finally completed the annual update of my ADC survey data. There’s a lot going on in the ADC field, so using scientific data only until March 2010 wasn’t going to be acceptable for much longer. Now the survey covers scientific ADC implementations reported all the way from 1974 until April/May 2011. Actually, I still have around 70 ADC papers from ESSCIRC 1975-1995 to read in order to make the survey backwards exhaustive, but those papers aren’t likely to change the content in this post. Therefore I’m not going to keep you waiting for this figure-of-merit status update any longer. Let’ get to the business:

Influence on state-of-the-art

With the current update, the survey data now covers 1550 unique scientific papers and we could expect some changes to the state-of-the-art registered by the ADC FOM-o-meter.

Standing Their ground

Not everything changes, though. Amazingly enough, the world record “Walden” or “ISSCC” FOM

set to 4.4 fJ by van Elzakker et al. three years ago [1] remains unchallenged. Quite impressive, indeed!

Pushing the envelope

The same SAR implementation by van Elzakker, also used to hold the state-of-the art “Thermal FOM”

for Nyquist converters, but a new record (7.6 aJ) was set by Hurrell et al. with a pipelined SAR ADC reported in December 2010 [2]. Observant blog readers may wonder why this design wasn’t already listed as state-of-the-art, since it was originally reported at ISSCC 2010. The answer is that the peak performance that nudged the state-of-the-art was measured at a very low (50 kHz), and that data point was not reported in the ISSCC paper – possibly in the slides. Since I wasn’t at the conference, any information shared in the slides was not available to me. Either way, congratulations to Christopher Peter Hurrell, and the rest of the team from Analog Devices UK and Ireland for this excellent design!

Finally, the overall best  reported by Pavan et al. [3], has been improved upon by a discrete-time DSM by Perez et al. [4] reporting a 2.7 aJ. Converter Passion is impressed by this significant contribution from Aldo Pena Perez and co-authors from University of Pavia, Italy. Congratulations!

Hall of fame

All changes are now registered on the Converter Passion ADC FOM-o-meter page – your one stop solution for monitoring the evolution of A/D-converter figures-of-merit – and you can still find the previous (and current) state-of-the-art in the newly opened Converter Passion Hall of Fame. [See the new top menu "Hall of Fame" for different halls.]

So, what do you think: Was this result to be expected, or did you find anything surprising in the update? What do you think is the best approach in order to finally beat the van Elzakker record and send it to the Hall of Fame? [Michiel and co-authors, you are obviously welcome to share your thoughts as well. Is your 4.4fJ record unbreakable?]

References

[1]    M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.

[2] C. P. Hurrell, C. Lyden, D. Laing, D. Hummerston, and M. Vickery, “An 18 b 12.5 MS/s ADC with 93 dB SNR”, IEEE J. Solid-State Circuits, Vol. 45, pp. 2647-2654, Dec., 2010.

[3]    S. Pavan, N. Krishnapura, R. Pandarinathan, and P. Sankar, “A 90μW 15-bit ΔΣ ADC for digital audio,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Munich, Germany, pp. 198–201, Sept., 2007.

[4] A. P. Perez, E. Bonizzoni, and F. Maloberti, “A 84dB SNDR 100kHz Bandwidth Low-Power Single Op-Amp Third-Order ΔΣ Modulator Consuming 140μW”, Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, USA, pp. 478-480, Feb., 2011.