Two years ago I set out to read, process and systematically analyze the data from every single scientific paper ever published in my main field – monolithic A/D-converter integration. One thousand five hundred scientific publications, and counting! It seemed, as they say like a great idea at the time, but it sure isn’t for the faint-hearted. No regrets, though.
I hope to be able to share some of the insights and knowledge gathered from this study right here on the blog. Not everything will be directly helpful in your design project of course, but there are other values in life, right? We’re just not sure exactly what they are yet …
In this post I want to highlight the steady increase in publications we have seen over the 36 years or so since Baldwin’s delta modulator . I believe it was the first monolithic ADC to be reported. (Please send me an email or post a comment here if you consider another publication to be the first.)
The plot above shows how the total amount of ADC publications have gone from a handful to over 100 scientific papers per year. (For practical reasons, some non-IEEE sources were not included in the count.) Thanks to the logarithmic “Y” axis we can easily see that the total number of ADC papers have grown exponentially for at least 20 years now, and there’s no sign of slow-down.
Personally I see this as good news. I am passionate about A/D-converters, and this means that my field is given more significance and there is also more experimental data available to use as reference points for your own work.
But … how do we cope with an ever-increasing influx of scientific reports? Are there any negative effects at all? Is it OK if every company needs to allocate one senior designer to just read all the publications? Is there an upper limit to how many ADC papers you want to see in publication 2020, or is 250 papers a significant improvement over 100? Would 500 be even better?
Personally I’m leaning heavily towards “the more, the merrier“.
But that’s me. What do you think?
See also …
 G. L. Baldwin, “A linear delta modulator/demodulator with 10 Mbit/s sampling rate”, Proc. of IEEE Solid-State Circ. Conf. (ISSCC), Philadelphia, USA, pp. 192–193, Feb., 1974.