ADC FOM: What is a good figure-of-merit?


No rocket science: A good FOM should simply reflect the merits of the ADC

So, what is a good figure-of-merit (FOM) for analog-to-digital converters (ADC)? What is technically sound? What makes a figure-of-merit relevant, and what is good practice when using it? I’ll not able to cover everything in one post, so the plan is to keep returning to this subject over a number of posts.

What is a figure-of-merit?

So, what is a figure-o-merit in the first place, and what should we expect from a good one? Well … Wikipedia currently defines it as:

“… a quantity used to characterize the performance of a device, system or method, relative to its alternatives. In engineering, figures of merit are often defined for particular materials or devices in order to determine their relative utility for an application. In commerce, such figures are often used as a marketing tool to convince consumers to choose a particular brand.”

Another quote from the Wikipedia entry touches on the question of relevance and proper use:

“When used in deceptive advertising, the deception lies more in the question of relevance rather than truth since the number quoted as a figure of merit may not be enough to determine performance when comparing products.”

As a consumer of whatever is marketed or assessed with a FOM – be it commercial ADC parts or scientific results – I also want to know that the FOM is designed so that anything awarded a state-of-the-art value is what actually has the best performance or is more useful to me. That is a well-conceived FOM. A well-conceived FOM also gives equal value to all objects that have equivalent performance with respect to whatever the FOM is supposed to measure, while an ill-conceived FOM can give widely different values for equivalent actual merits. In short, I would say that:

A good figure-of-merit should accurately reflect the merits of the ADC in the context and for the purpose which the figure-of-merit is used.

You are welcome to share your thoughts on this. What would you expect from a good FOM? What criteria do you use to identify an ill-conceived FOM?

Purpose & context

A figure-of-merit is used for a purpose and in a context. Common purposes include:

  • Marketing
  • Product performance comparison
  • Comparison of scientific achievement
  • Identifying the best component for a particular task

The context is also important. If you want to apply a FOM to a set of commercial part specifications to find out which part is the best for your current project, then you can define pretty much any FOM expression you’d like, as long as you know it will help you detect the best circuit. The context is local – your project and your organization. You only have to convince your project team and perhaps the steering group that the FOM is technically sound and will do the job.

If, on the other hand, you wish to propose a FOM that can be universally applied to compare the merits of widely different circuits, the context is global. The demands will be higher – both with respect to the mathematical expression and your ability to convince others that the FOM is sound. We will focus on this latter case.

ADC FOM vs. CMOS node. This FOM improves with scaling.

Universal comparison of merits in a global context

Universal comparison of merits can be divided by at least two major purposes: (I) product comparison and (II) comparison of scientific achievement. When comparing the merits of a product, it doesn’t matter if a FOM is biased towards certain design parameter values. If the FOM correctly represents end user satisfaction, it is irrelevant whether or not you can always achieve a better FOM by reducing power, increasing the voltage supply, or by using a more recent manufacturing technology. If new technology makes the design easier each year, who cares? For the end user it doesn’t matter how easy or hard it was for the engineers to develop the product – as long as the FOM measures how good the product is for the user, it is all well.

When a FOM is used to measure or claim scientific achievement and progress, it does matter if certain corners of the parameter space always gives the best results. Then the FOM becomes a measure of how close you are to that corner, rather than a measure of some universal achievement. This is actually the case with the most commonly used FOM today

F_{A1} = \dfrac{P}{2^{ENOB} \times f_s}

It was shown in [1] that a distinct feature of F_{A1} is that it improves with every step of CMOS scaling. Roughly F_{A1} improves by 100 times for every 10 times of process scaling, as seen in the FOM vs. CMOS node plot above. In practice, it means that organizations that have the possibility to use the latest technologies will always win the race with respect to F_{A1} , while those that refine their design in other ways (without moving to a newer technology node) have practically no chance. Its usefulness as a universal measure of scientific achievement in power-performance trade-off can therefore be questioned.

That said, it should be understood that designing in deeply scaled nanometer technologies is certainly not without challenges. Quite the contrary – it has many design challenges, and it is a scientific or engineering achievement to break new ground and design ADCs in the most recent CMOS nodes. But the point here is the particular FOM F_{A1}  and that process scaling almost automatically improves it. A research group that develop innovative architectures or circuit techniques that improve the power-performance trade-off within the same node is therefore much less likely to publish state-of-the-art F_{A1} values than a group that focus on the problems of porting its design to newer technologies. Hence F_{A1} , the most commonly used FOM today, heavily promotes the use of new process technology, and this should be understood when comparing the FOM reported in different papers.

I also want to clarify that I’m not suggesting that those that have defined the state-of-the-art evolution of F_{A1} have effortlessly surfed the wave of CMOS scaling. Many, most, or all of these designs have reached state-of-the-art through a combination of technology scaling and innovative techniques for power reduction. As an example, the design by van Elzakker et al. [2] currently listed as state-of-the-art on the FOM-o-meter page, combines the advantages of 65 nm technology with a low-energy multi-step switching charge-transfer technique to reach a truly impressive result.

Industrial and scientific relevance

As discussed above, a FOM may have relevance for comparing the performance of commercial products without being suitable for comparison of scientific achievement. In my opinion, F_{A1} has industrial relevance only to the extent that it measures what the buyers truly want from an ADC part. I’m not in a position to fully assess whether F_{A1} is representative of the market demand, or if the market has simply been taught by ADC vendors that “this is what you really want” 🙂 so now the sourcing people keeps asking for it. It would certainly be interesting to hear your thoughts on that – both from a sourcing and from a vendor perspective.

Regarding scientific relevance, F_{A1} , a.k.a. the “ISSCC FOM” has some redeeming features in that it can be shown that an ADC with state-of-the-art F_{A1} is indeed highly optimized with respect to energy per sample. On the other hand, F_{A1} displays such a strong correlation with many design parameters, that it can also be shown that a state-of-the-art F_{A1} can only ever be achieved at certain sweet spots and golden corners within the design parameter space. Its almost canonical status as a global measure of scientific achievement, and possibly even criteria for publication, is therefore in my opinion questionable. Or at least something that needs a serious debate. I’m sure that many of my blog readers have an opinion too, and it would be great to hear what you think. It is no problem if you have a different view, I’d like to hear it anyway. Perhaps you can bring me back to “the narrow path” 😉 …

I hope to get back with more details on sweet spots and corners in future posts, but for now the FOM vs. CMOS node plot can serve as illustration of a “golden corner” with respect to process technology.

FOM discussions in the literature

There are only a few literature references to this post, simply because I’m not aware that any longer discussion of the topic has taken place anywhere. But if you are aware of any scientific papers, business magazine articles, application notes or web pages treating the title question of this post – “What is a good ADC FOM?” – then I’d be very happy to hear about it and to include references to them here. Please use the comment function, or email me.

Bult includes in his ESSCIRC 2009 paper [3] a brief but good discussion on how the current scientific competition is centered around F_{A1} , and its consequences on power dissipation reporting practices – a topic I will return to in a future post. Bult also reflects on the relevance of 2^{ENOB} and 2^{2\times ENOB} in view of observed and expected correlation between ENOB and P in actual circuits. In Carsten Wulff’s Ph.D. thesis [4], there is a discussion of figures of merit, and Murmann also discusses the relevance of 2^{ENOB} and 2^{2\times ENOB} briefly in his CICC 2008 paper [5].

ADC FOM DIY-kit

Now, if after reading this far you are tempted to try your hand at designing your very own and much better ADC FOM, then you have the perfect DIY-kit here at Converter Passion. It will help you to shape and define almost any FOM of your liking. You can always start building it from scratch if you feel adventurous, but why not start with the “Mother of all FOM”, and the generic FOM classes I’ve put together for you.

Enjoy, and don’t forget to share your views on ADC figures-of-merit with the rest of us.

And … if you invent a smashing ADC FOM, or already have published one that I’ve missed, be sure to post it in the comments.

Let me know if you want help getting the WordPress LaTeX to work. It can be used in the comments as well. Here’s an on-line LaTeX equation editor that makes life easier. Because the WordPress LaTeX parser is much less forgiving, the code sometimes need some final polishing before it renders correctly.

References

[1] B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.

[2] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/conversion-step 10b 1MS/s charge-redistribution ADC”, Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008, IEEE.

[3] K. Bult, “Embedded analog-to-digital converters,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Athens, Greece, pp. 52–60, Sept., 2009.

[4] Carsten Wulff, Efficient ADCs for nano-scale CMOS Technology, PhD Thesis, Norwegian University of Science and Technology, Trondheim, Norway, Dec. 2008.

[5] B. Murmann, “A/D converter trends: Power dissipation, scaling and digitally assisted architectures,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 105–112, Sept., 2008.

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5 responses to “ADC FOM: What is a good figure-of-merit?

  1. Pingback: Going to Italy … Yes, Yes, Yes!! | Converter Passion

  2. Pingback: Is A/D-converter research becoming a purely academic exercise? | Converter Passion

  3. Pingback: Best know SAR ADC design

  4. Johan Dijkhuis

    For commercial applications there are 2 points very important, assuming the ENOB and sampling rate are set by the system architecture:
    1) how much power does it consume
    2) how much silicon area does it take
    There are of course lots of other requirements to embed a particular ADC in a certain system (supply voltage, PSRR, etc.) but most can be translated in the above 2 for a certain system. Note that most published FOMs take 1 into account, but 2 not. What I would like to know as a practising engineer is what topology to use for my design, and how critical it will be (time needed to make it work). According to the FA1 FOM I can trade the power consumption vs sampling rate e.g. by putting 2 ADC’s parallel with the clock shifted. However, it would also be very interesting to have a “scaling law” to compare ADCs in different CMOS nodes, to decide which is better (as example), a 1 mA ADC in 90 nm CMOS or a 400 uA ADC in 65 nm CMOS, if scaled to 40 nm CMOS (assuming that is the process where I want to make my IC). Of course there is no guarantee that this process scaling is the same for different types of ADC (e.g. SA vs sigma delta vs pipeline).

    Another interesting FOM is to compare it to a theoretical limit. e.g. a capacitive SA ADC will exhibit kT/C noise, limiting its dynamic range. Even with perfect switches it will not be able to do better than that. Other ADC types will also have theoretical limitations. If we know how far we are from this theoretical limit it is easier to predict if a particular ADC will still benefit from scaling or not. Probably some ADC types are much closer to their limits than others.

  5. Thank you for a great and insightful comment, Johan. You mention a lot of things that are still quite undertreated. I hope to be able to post some results from investigations in the directions you are suggesting later, but let me for now just give a few comments:

    You are right that most FOM do not look at area. In my opinion, area vs. performance/scaling/architecture is very underexplored so far. There should be a lot of good research topics there. I made a first attempt looking at it empirically in my ECCTD 2011 paper “Area Efficiency of ADC Architectures“. I’m the first to acknowledge that there are many more angles to look at, but at least it can be used as a starting point or empirical reference for future works. Based on the global empirical distribution of Area vs. ENOB performance, I assumed a normalized area measure (or “FOM” if you will) A_Q = A/(2^ENOB). I didn’t put 2^ENOB there because “that’s what people usually throw into FOMs” but because it actually described the overall boundary data-fit quite well. To my joy, and also surprise, this leveled out the state-of-the-art area (or A_Q) boundaries quite well without any further normalization parameters having to be introduced. Flattened versus ENOB, obviously, but also vs. sampling rate, noise floor (i.e., simultaneous combination of fs and noise/resolution), and even removed most of the influence of scaling. Even when breaking it up by architecture, it held up quite well, although it was obvious that some architectures had a different slope, and a modification to scale by 2^(alpha*ENOB) where alpha is architecture-dependent would be an improvement. Again, it’s not the final word on area-vs-performance, but if you didn’t already, I think it’s worth a read.

    Power efficiency has been treated a bit more. Theoretical limits have been derived, e.g. by Sundström/Svensson/Murmann, and then we have the P/fs vs SNDR plot in Murmann’s online survey, etc. In one of my IWADC 2011 papers “An empirical approach to finding energy efficient ADC architectures” I looked at Es = P/fs vs. ENOB separated by architecture. Like you suggest above, I compared to some kT/C limits. This one too is only a first attempt, and there’s a lot more to be investigated. For example dependency on scaling, fs etc. Also the theoretical limits for individual architectures. At least it confirms what we already knew – that different architectures seem to have different power limits.

    I haven’t yet combined these two works. They also take more of a “global” look at the data scatter. I felt that was the logical place to start, after which one can refine it by adding more theoretical analysis and/or check how the results change vs. scaling, speed, architecture, etc.

    If you want to contribute with anything you’re most welcome.

    Finally, I can confirm what you assume above, that different architectures respond differently to scaling. Partially it could be due to different architectures being used at different resolution grades, but my impression is that there are also differences within the same resolution range. Again, loads of different research/studies to be done here.

    Life’s too short indeed …

    BTW: Bechen et al. proposed a FOM that should be more scaling-neutral. Its labeled F_E1 in my list (https://converterpassion.wordpress.com/generic-adc-fom-classes/). According to an empirical evaluation shown in my second IWADC 2011 paper (“Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance“), they succeed quite well – although the plain old “Thermal FOM” (F_B1) is almost as flat.

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