Going to Italy … Yes, Yes, Yes!!

I will actually try to make some sense out of plots like this one during the IWADC.

The review results from IWADC have now reached me and, yes … it looks like I’ll be going to Orvieto this summer to present two ADC papers. It will be great fun to go. Now, the only thing that I have to do to ensure a happy stay is to prevent my wife from realizing just how beautiful the city of Orvieto and the surrounding area really are, otherwise she’ll drag me out of geek heaven (discussing data-converter issues with like-minded people in windowless conference rooms with dimmed lights) and force me to see magnificent medieval buildings, and perhaps some stunning views from the region of Umbria. Now, who would want to do that? 😉

The two papers I’ll present are titled “An empirical approach to finding energy efficient ADC architectures” and “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance“. The first paper takes a look at the entire body of measured and scientifically published monolithic ADC implementations in order to determine the energy-efficiency of different architectures across the entire resolution range from 2 to 22 effective bits. An efficiency hierarchy of ADC architectures is extracted from the empirical data, and key low-power enablers are identified by a more specific review of the 15 most power-efficient ADCs ever reported. So, if you want to know if SAR ADCs dissipate less power than their pipeline counterparts, or what the difference is between flash and folding ADCs in terms of energy efficiency, this is a paper for you. If you come to IWADC you’ll see the scatter plots explained in real life. Trust me, you don’t want to design ultra-low-power ADCs without knowing what’s in this paper. [I could of course be biased … ;-)]

Believe it or not – there is some meaning to all of this too. Hopefully it will all be clear before you leave Orvieto.

The second paper reviews the practice of using figures-of-merit (FOM) to compare measured ADC performance – a topic you may recognize from this blog. In fact, the more tutorial-oriented introduction and background parts of the paper include the generic FOM and the generic FOM classes you may have seen already, while the core contribution in the paper is the analysis of FOM properties by applying them to real data. More specifically, their correlation with the two design/implementation parameters ENOB and CMOS node is observed and discussed. The entire body of measured and scientifically reported monolithic ADCs is once again used to support the analysis. Sensitive listeners should be warned about this paper – your trust in a certain FOM may be somewhat challenged during presentation 😉

Now, didn’t that make you at least a bit curious?

And how about you? Any plans to go to IWADC 2011? Any contributions you wish to mention? Does the phrase “going to Italy” sound nice to you as well?

5 responses to “Going to Italy … Yes, Yes, Yes!!

  1. Very curious! And ‘fancy’ plots!
    Wish you a nice stay there!

  2. Thanks, Dai!
    They look ‘creative’, don’t they?
    Hope to see you again soon. Perhaps ECCTD 2011 in Linköping is a safe bet?

    • Speaking of that! Only one week left for paper submission to the ECCTD 2011 .

      May I however be a bit curious regarding “the entire body of measured and scientifically published ADC implementations”. So what happened before 1970-early? I remember once seeing the first “integrated” 8-bit ADC somewhere on a picture. Quite some machine there. How did it all start? What was the egg? (Or the chicken?)

      • Yes … ECCTD. I’m actually sweating with a manuscript right now. Hope to be able to finish something in time.

        Phrases like “The entire body …” should probably be surrounded with tons of disclaimers, but I’m getting brave (or was it careless?). First, I’ve now inserted “monolithic” into the phrase. The, I should mention that I haven’t [yet 😉 ] scanned every possible source of papers, but close to everything that is likely to have anything that could change the “state-of-the-art enevelopes” that I use quite frequently in my empirical approach.

        In the “early days” of our field, they did a rather smooth transition from discrete to monolithic, where for example they’d just integrate the comparator, and have a SA(R) register off-chip on PCB, or on a second IC/die. Quite understandable, but it leaves a stringent type like myself with some trouble deciding where to draw the line between ‘monolithic’ and not (that is, where my data starts).

        The way I defined it, there wasn’t anything before 1973 or 1974.

        If anyone knows otherwise, I’m more than happy to hear about it.

        [And if it should so happen that anyone from “the early days” ever read this blog, please make contact. It would be very interesting to hear your stories from back then.]

  3. Pingback: Connect with Converter Passion at IWADC 2011 | Converter Passion


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