ADC Survey: Spring 2011 update on FOM state-of-the-art

Experimental ADC data emerge like flowers in the spring.

Now I have finally completed the annual update of my ADC survey data. There’s a lot going on in the ADC field, so using scientific data only until March 2010 wasn’t going to be acceptable for much longer. Now the survey covers scientific ADC implementations reported all the way from 1974 until April/May 2011. Actually, I still have around 70 ADC papers from ESSCIRC 1975-1995 to read in order to make the survey backwards exhaustive, but those papers aren’t likely to change the content in this post. Therefore I’m not going to keep you waiting for this figure-of-merit status update any longer. Let’ get to the business:

Influence on state-of-the-art

With the current update, the survey data now covers 1550 unique scientific papers and we could expect some changes to the state-of-the-art registered by the ADC FOM-o-meter.

Standing Their ground

Not everything changes, though. Amazingly enough, the world record “Walden” or “ISSCC” FOM

F_{A1} = \dfrac{P}{{2}^{ENOB}\times f_{s}}

set to 4.4 fJ by van Elzakker et al. three years ago [1] remains unchallenged. Quite impressive, indeed!

Pushing the envelope

The same SAR implementation by van Elzakker, also used to hold the state-of-the art “Thermal FOM”

F_{B1} = \dfrac{P}{{2}^{2ENOB}\times f_{s}}

for Nyquist converters, but a new record (7.6 aJ) was set by Hurrell et al. with a pipelined SAR ADC reported in December 2010 [2]. Observant blog readers may wonder why this design wasn’t already listed as state-of-the-art, since it was originally reported at ISSCC 2010. The answer is that the peak performance that nudged the state-of-the-art was measured at a very low f_{in} (50 kHz), and that data point was not reported in the ISSCC paper – possibly in the slides. Since I wasn’t at the conference, any information shared in the slides was not available to me. Either way, congratulations to Christopher Peter Hurrell, and the rest of the team from Analog Devices UK and Ireland for this excellent design!

Finally, the overall best F_{B1} reported by Pavan et al. [3], has been improved upon by a discrete-time DSM by Perez et al. [4] reporting a 2.7 aJ. Converter Passion is impressed by this significant contribution from Aldo Pena Perez and co-authors from University of Pavia, Italy. Congratulations!

Hall of fame

All changes are now registered on the Converter Passion ADC FOM-o-meter page – your one stop solution for monitoring the evolution of A/D-converter figures-of-merit – and you can still find the previous (and current) state-of-the-art in the newly opened Converter Passion Hall of Fame. [See the new top menu “Hall of Fame” for different halls.]

So, what do you think: Was this result to be expected, or did you find anything surprising in the update? What do you think is the best approach in order to finally beat the van Elzakker record and send it to the Hall of Fame? 😉 [Michiel and co-authors, you are obviously welcome to share your thoughts as well. Is your 4.4fJ record unbreakable?]


[1]    M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.

[2] C. P. Hurrell, C. Lyden, D. Laing, D. Hummerston, and M. Vickery, “An 18 b 12.5 MS/s ADC with 93 dB SNR”, IEEE J. Solid-State Circuits, Vol. 45, pp. 2647-2654, Dec., 2010.

[3]    S. Pavan, N. Krishnapura, R. Pandarinathan, and P. Sankar, “A 90μW 15-bit ΔΣ ADC for digital audio,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Munich, Germany, pp. 198–201, Sept., 2007.

[4] A. P. Perez, E. Bonizzoni, and F. Maloberti, “A 84dB SNDR 100kHz Bandwidth Low-Power Single Op-Amp Third-Order ΔΣ Modulator Consuming 140μW”, Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, USA, pp. 478-480, Feb., 2011.

8 responses to “ADC Survey: Spring 2011 update on FOM state-of-the-art

  1. Ok, so I have some questions and both sets of quesgtions might be a bit “silly” or even naive at first, but I think they make sense…

    (1) What happens if you include the $ into it? Or say project development time (effectively proportional to $)? What is the reported chip cost for the different ADCs? Is good performance tightly connected with expensive processing/board/package/bonding? Can the cost be brought into the equation? I’m thinking ENOB ~ matching ~ Area ~ Cost, or so.

    (2) What is the momentum (or maybe inertia)? It’s expressed in the formula already in some sense, but it is a multidimensional space. If I want to go from ENOB = 7 to ENOB = 8, I can choose to increase power or decrease frequency or both or etc., etc. Which one should I choose?

  2. Michiel and co-authors, you are obviously welcome to share your thoughts as well. Is your 4.4fJ record unbreakable?

    Making an ADC with a Walden-FOM below 4.4 fJ is perfectly feasible, all you need is:
    – A well equipped lab
    – An expensive MPW
    – A couple of man-months of a design-team with the right mixture of know-how and getting-things-done mentality

    In my opinion the real question is: who will do it first?

    For an industrial design many things are important, but Walden-FOM isn’t really one of them. Still I am convinced that a lower FOM will appear in industry, a well-implemented low-power design in 32 nm CMOS could be sufficient.

    For academic low-power methods, novelty seems to be more important than usefulness. The problem is that many novel low-power methods are not worth the overhead and actually increase power consumption. Still, there are plenty of untested methods left and I have no doubt that there will be a researcher who can make a good ADC out of one of them.

    Hiding some functionality behind a curtain always helps. For example, overhead for control and calibration just vanishes when you integrate it into a PC or into the sea of gates. There is a huge gray area with tricks like this, some of them are discussed in the earlier “What is an ADC?” post.

  3. @jjwikner: (1)
    Yes, various cost measures would be interesting to include [BTW Michiel: forgot?? Me? 🙂 That’s why I tactically put a D in the expression (essentially to claim everything) … here we could say “D for dollar” 😉 … ].

    As you mention, area is a cost that translates to $. I’ve actually completed some area-related work which I hope to get published soon.

    Including development time [although never reported in data sheets, and almost never in papers] would make a lot of sense for industry, and most likely favour architectures and solutions that reach a reasonable performance while being suitable for auto-generation. That would be valuable information to companies, I guess. Unless companies suddenly start to give out design times, I guess each company would be restricted to analyzing their own product portfolio with such FOM.

    Similarly, board & bonding is difficult to analyze from open sources, but package and processing is fully possible to observe without writing NDA:s.

    I don’t have the quantitative answers to your (1) to share here, but I do have most of the data necessary to do the investigation. So, any company that wants to know can just pick up the phone and call me at ADMS Design AB and order a custom investigation. Very worthwhile if you wish to approach your ADC pricing strategy systematically.

    (Sorry about the plug)

  4. @jjwikner: (2)

    Inertia … interesting angle. The answer depends heavily on what FOM we’re talking about. If we mean “The FOM”, then the example you mention is actually a move towards the global optima. So in that particular case, the penalty might be less than what the FOM expression makes you believe.

    Both my IWADC papers shed some light on this, but I don’t want to spoil the fun for those going to the IWADC 2011 in five weeks from now by telling everything here. Perhaps we can come back to this matter after IWADC?

    In general, if you don’t care about any absolute performance parameters, but are just aiming to improve “The FOM”, then I’d suggest to go for lower or same power, then adjusting the other parameters to what you can possibly achieve.

    But, like you say … its a multidimensional design space. When you have an actual set of ADC specifications, one needs to look at the data with that particular design target in mind.

  5. @Michiel:
    It seems quite promising for the ADC field, then. Both academia, industry, and the “magicians” will have good chance to succeed.

    I agree with you that its only a matter of time before someone will. Particularly since the Walden-FOM improves with scaling, the 32nm design you visualize seems a likely candidate.

    The “magicians” tool box of trickery that you bring up is an important discussion that I’ll try to encourage here on the blog. Particularly the tendency to avoid reporting this and that part of the power dissipation, all in the interest of reporting a better FOM. I wouldn’t mind so much how individual authors choose to claim their FOM as long as all the power contributors were clearly reported in the paper. Then anyone disagreeing with their FOM calculation practice could simply add the omitted power and get what they feel is the “correct” FOM out of the paper [*]. But the “power omitters” tend to not volunteer this information at all in their papers, thus preventing their results from being consistently compared with prior art. While it may give the authors some short-lived advantage, it also renders their contribution much less meaningful to the scientific community, because it can’t be accurately put into the context of the collective body of ADC research. And that’s a real shame when someone may have spent as much as a full year of their life on a design.

    In my opinion, this reporting trend should be nipped in the bud before it “blesses” the world with a decade’s worth of inconsistent and partially useless research data. [Now I really got going … ;-)]

    Those of us who review papers could make a real difference here. “Mandatory change” would be the perfect tool to do the “nipping”.

    Perhaps I’m too radical – what do you think?

    [*] Omitting I/O-power is acceptable for me in this SoC age. Ideally, though, I’d like to see it reported for the sake of backwards compatibility of reported results, but not necessarily included in the FOM claim.

  6. Pingback: Is A/D-converter research becoming a purely academic exercise? | Converter Passion

  7. Pingback: ADC Survey: Spring 2012 update on FOM state-of-the-art | Converter Passion


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