Reader question(s): Novelty of folding amplifier ADC architecture, big houses approach to external innovations, and academic vs. commercial specs

Blog reader Cole posted a question in the Q&A section, and I felt it was well worth a separate post:

Hi Dr. Jonsson, I am wondering the following things in general about the ADC industry:

–Are folding amplifiers a new concept? Why when I look at the TI website, for example, they do not sell any ADCs with a folding amplifier architecture?
–How open are the big houses to outside designs? If a small design house comes up with someone innovative, do the big houses adopt, buy-out, or ignore the small houses?
–What is the main difference between academic specs and industrial specs? How would I “convert” between the two? It seems like when I read academic papers, they claim high speeds at a certain bitrate, but industrial numbers all seem a bit more conservative (i.e. MSPS rather than GSPS).

As you can see, there are several interesting questions in there. What do you think? How hot are folding ADCs today? Do you have any experience from start-up innovation in relation to the big companies? How do you translate between data sheet specs and academic paper performance?

Anyone from “the big houses” wish to comment? How would you handle great innovations emerging in a small start-up external to your company? Adopt, buy-out or ignore? And how should we view commercial data sheet specs compared to scientific papers? Should we even try to “translate” between the two, or are these better seen as parallel universes?

3 responses to “Reader question(s): Novelty of folding amplifier ADC architecture, big houses approach to external innovations, and academic vs. commercial specs

  1. Cole: I will take it in smaller chunks:

    I’m not sure if with “folding amplifiers” you mean something different than the folding circuit in a typical folding ADC, but at least I can say that folding type ADCs are not new. The first monolithic integration reported scientifically was to the best of my knowledge [1], which was followed up with a journal version (IEEE Journal of Solid-State Circuits) the following year.

    The total number of folding ADC papers in major IEEE ADC sources seem to have settled to no more than five per year. Since the total number of ADC publications per year is steadily increasing, the relative amount of folding ADCs has shown a steady decline – from a peak 16.7% (1/6) in 1983 to 4.5% of the population in 2010. It could also be mentioned that the accumulated total is slightly above 60 papers describing monolithic folding ADC implementations, or around 4% of all such publications.

    While first impression is that the folding architecture then has been abandoned by mainstream ADC researchers, it could also be interpreted as the folding architecture being underexplored to this date. I could suspect the latter. Recent publication such as [2] indicate that an MSB folding stage followed by a low-power LSB stage can yield a very low energy per sample, at least at lower resolutions. It will be shown in greater detail in my upcoming IWADC paper [3].

    So the chance to make a good innovation related to folding or folding-hybrid architectures is just as good as for any of the more popular architectures.

    /* End of first chunk */

    [1] R. E. J. van de Grift, and R. J. van de Plassche, “A monolithic 8-bit video A/D converter”, Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Lausanne, Switzerland, pp. 57-60, Sept., 1983.

    [2] B. Verbruggen, J. Craninckx, M. Kujik, P. Wambacq, and G. Van der Plas, “A 2.2mW 5b 1.75GS/s folding flash ADC in 90nm digital CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 252–253, Feb., 2008.

    [3] B. E. Jonsson, “An empirical approach to finding energy efficient ADC architectures,” Accepted for presentation at 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, June 2011.

  2. Whether or not “academic papers claim high speed while industrial numbers seem more conservative (MSPS rather than GSPS)” probably depends where one looks, and how you look at it:

    First of all, product specs in data sheets need to resemble the typical performance in volume production, while the performance reported in scientific papers can – depending on the author’s approach – be from the best pick within the 20-200 MPW samples received. Scientific implementations can also loose a lot of overhead needed to make a product robust in volume production and to the end user. All other conditions equal, purely scientific ADCs can therefore be expected to be slightly faster (less parasitics) than the stated “typical” performance of similar commercial products, and also use less power because some of the overhead circuitry or extra design margins in products lead to an increase power dissipation.

    Secondly, even if TI doesn’t have GSPS ADCs (They actually have for example the 1GSPS, 12-b ADS5400 ), there are others. National has a family of up to 12-b, 3.6GSPS ADCs (and maybe that was one reason for TI to buy National), Maxim has three, and e2v has a family of converters going up to 10-b, 5GSPS. The fastest scientific ADC that I’m aware of run at 40GSPS, but for a truly insane speed, you can look at the Fujitsu CHAIS ADC with 8-b nominal resolution at 56GSPS.

  3. As to the willingness of big houses to buy innovative solutions, it would be best if the big companies answered themselves. But solutions for removing artifacts from time-interleaving is one example of technology that several big companies have been willing to shop externally:

    I have no information about the actual business models used, but Analog Devices appears to have licensed such technology from V-Corp, while several companies, including LeCroy, Intersil, and TI, appears to have in one way or another utilized the interleaving solutions from Swedish company SP Devices (where several good friends of mine work, BTW. Hi all!).

    [Information is from the V-Corp and SP Devices web pages, respectively]


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