Well folks, its the time of year when an A/D-converter survey update is due. Since a significant effort is still invested in the quest for ever-improving figures-of-merit (FOM), I’ll start by firing up the Converter Passion FOM-o-meter and apply it to the body of ADC science. The latter is here approximated by my pet project – the ADC performance survey.
Including the papers added since last year, the updated survey now has 3628 experimental data points extracted from 1708 scientific papers published between 1974 and April/May 2012. The number of unique ADC implementations will be slightly less, since some papers are full-length versions of conference contributions. The source publications monitored are listed here.
What a difference a year makes …
… or not?
Can you believe this: With all the current competition to get a great ISSCC/Walden-FOM
the state-of-the-art (4.4 fJ) reported by van Elzakker et al. at ISSCC four years ago  is still number one. Their design really went the extra mile with respect to getting a low energy per sample, and I guess that paid off big time. Well done!
As Michiel commented, it is just a matter of time before someone goes below 4.4 fJ. This is also reflected in the scientific output over the last twelve months. Although the current world record didn’t change, there are several designs that reported an < 10 fJ, and that’s not bad either. They are:
|FOM [fJ]||Speed [S/s]||ENOB||Architecture||1st Author||Ref|
The most striking feature is probably that they are all SAR ADCs. Secondly, while they are all impressive efforts, the one that stands out a bit is the design by Verbruggen et al. It maintains a sub-10fJ FOM at a significantly higher sampling rate (250 MS/s) while also reporting the highest resolution .
Although it’s beyond the scope of this post, it can be good to keep in mind that there are other aspects to factor in than simply the FOM value when analyzing energy efficiency. It was pointed out by Verbruggen  that previous ultra-low FOM ADCs have been reported only at rather low sampling rates or moderate resolution. It is a greater challenge to maintain a low for high sampling rates. Hence, pragmatic limits to the state-of-the-art are speed-dependent. It has also been shown that the limits are both scaling- and resolution-dependent [7, 8], so a perfectly fair comparison between designs is difficult to make. I can pretty much guarantee that I’ll get back to this topic in the future, but for the remainder of this post we’ll just look at the raw FOM numbers as they are.
It would have been boring to read another 100+ papers and still have nothing new to report, so I’m very glad to see that the so called “Thermal FOM”
has been improved by over a factor of two through the switched-opamp (SO) based ∆∑ design reported by Xu et al. . Previous state-of-the-art – 2.7aJ reported by Perez et al.  – will assume its well-earned place in the Hall of Fame, while we applaud the 1.1 aJ achieved by the Chinese team from Zheijan University and Analog Devices, Shanghai. You’re the best now. Enjoy!
Thermal FOM for Nyquist ADCs
There has also been some evolution among the Nyquist ADCs: The 250MS/s SAR ADC by Verbruggen et al. mentioned above, is actually the new Thermal-FOM champion for Nyquist ADCs as it nudges the previous record  from 7.6 to 6.6 aJ. The authors are with imec, Belgium, and Renesas Electronics, Japan. Congratulations!
Old and new winners are always found in the halls of fame for Thermal and Walden FOM, respectively. If you are only interested in checking for the current leaders, the FOM-o-meter gives you both with a single click.
As always: I do believe the information here is correct, but if I’ve misrepresented anyone or forgotten to mention someone that should have been included, just send me an email or post a comment below.
 M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.
 R. Sekimoto, A. Shikata, T. Kuroda, and H. Ishikuro, “A 40nm 50S/s – 8MS/s Ultra Low Voltage SAR ADC with Timing Optimized Asynchronous Clock Generator,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Helsinki, Finland, pp. 471–474, Sept., 2011.
 T.-C. Lu, L.-D. Van, C.-S. Lin, C.-M. Huang, “A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/Conversion-Step SAR ADC for Biomedical Applications,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.
 P. Harpe, Y. Zhang, G. Dolmans, K. Philips, and H. De Groot, “A 7-to-10b 0-to-4MS/s Flexible SAR ADC with 6.5-to-16fJ/conversion-step,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 472–473, Feb., 2012.
 A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS,” IEEE J. Solid-State Circuits, Vol. 47, pp. 1022–1030, Apr., 2012.
 B. Verbruggen, M. Iriguchi, and J. Craninckx, “A 1.7mW 11b 250MS/s 2× Interleaved Fully Dynamic Pipelined SAR ADC in 40nm Digital CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 466–467, Feb., 2012.
 B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.
 B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, June 2011. [PDF @ IMEKO]
 J. Xu, X. Wu, M. Zhao, R. Fan, H. Wang, X. Ma, and B. Liu, “Ultra Low-FOM High-Precision ΔΣ Modulators with Fully-Clocked SO and Zero Static Power Quantizers,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.
 A. P. Perez, E. Bonizzoni, and F. Maloberti, “A 84dB SNDR 100kHz Bandwidth Low-Power Single Op-Amp Third-Order ΔΣ Modulator Consuming 140μW,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, USA, pp. 478-480, Feb., 2011.
 C. P. Hurrell, C. Lyden, D. Laing, D. Hummerston, and M. Vickery, “An 18 b 12.5 MS/s ADC With 93 dB SNR,” IEEE J. Solid-State Circuits, Vol. 45, pp. 2647-2654, Dec., 2010.