ADC research trends: CMOS node adoption

Figure 1. Distribution of CMOS nodes used for scientific ADCs over time. Color represents number of publications. The early adopter state-of-the-art data points are superimposed along with a scaling trend estimated from 1995–2011 data.

ADOPTING NEW TECHNOLOGY: The rate at which scientific ADC implementations migrate to newer CMOS technology is discussed in this post. It was previously observed in [1], using a more one-dimensional approach and data until March 2010. Here, updated ADC survey data is used, and the 2-D distribution of scientific ADC implementation papers over CMOS node and publication year is analyzed. The result is illustrated by the “heat contours” in Fig. 1. Starting with dark blue, the colors represent paper counts of 0, 1, 2, 5, 10, 15, …,  and 40/year, respectively.

Observation of technology adoption

Figure 1 illustrates several key aspects of how the scientific ADC community has adopted new process technology:

  • The lower edge of the contours represents the early adopters. It defines the state-of-the-art scaling front for ADCs. In [1] it was estimated that this front scaled by an average factor of two every 5.4 years until 1995. After 1995, the adoption rate increased to 2 X every 3.75 years, which is illustrated by the exponential trend fit. The data points used for the trend estimations are superimposed onto the contour plot.
  • The “center-of-mass” illustrates the average node-adoption by the main body of ADC scientists. Although a highly subjective visual estimation, my impression is that the mainstream adoption rate is higher from 180 nm and below. What do you see?
  • The horizontal extension of each node reveals its lifetime in scientific publications. Popular nodes can remain active for well over a decade. Therefore, the correlation between CMOS node and publication year is weak. In other words: you can’t make a good observation of the effects of scaling by simply looking at how something evolves over time. Because of the long lifespan of major nodes, they also have time to undergo a maturing process as the collective understanding of how to best use the node accumulates. ADC performance vs. scaling and the concept of maturing nodes was treated in [2].
  • 180 nm appears to be the all-time favorite node for CMOS ADC designs to this date. This was also observed in [2].
  • Nodes as old as 0.35µm are still active in publications.

Adoption rates, systems on chip, and the scaling gap

Traditionally, there has been a lag – or “scaling gap” – between analog/mixed and digital ICs. Digital ASICs have nearly always benefited from using the most recent technology, whereas analog/mixed ICs have faced new design challenges for every step of scaling. Consequentially, ADC designers have lingered in older, or custom, technologies where they knew they could meet the spec, while digital ASIC designers switched to new nodes as soon as possible. This approach was acceptable – perhaps even optimal – as long as ADCs were used as stand-alone components. Moving into the age of the SoC (system on chip), the scaling gap is increasingly unacceptable. The A/D-converters must be on the same chip as the rest of the circuit, and migrating the digital parts backwards is almost never an option. Therefore the gap must close.

Personally, I believe that this SoC-driven need to close the scaling gap is the most likely explanation for the increased rate of early adoption observed in [1] and mentioned above. If you have any other suggestions, please share them with us in the comments below.

Future ADC scaling

If the current scaling trend should continue, early adopters would implement ADCs in 5.5 nm CMOS by 2020. As mentioned in [1], that is well below the technologies predicted available for RF/AMS design by 2020 [3]. As the gap closes between analog and digital, we will therefore see a slowdown in adoption rate.

In fact, the RF/AMS data in [3] suggests that the scaling gap is already quite small. A minimum L = 24 nm for HP logic in 2011 should be compared with the most deeply scaled ADC in 32 nm CMOS, presented by a team from Intel [4]. Since a small lag between digital and RF/AMS ASICs (as well as between technology “year of production” and ADC “year of publication”) may be inevitable, a slowdown in early-adoption ADC scaling could be just around the corner.


[1] B. E. Jonsson, “A survey of A/D-converter performance evolution,” Proc. of IEEE Int. Conf. Electronics Circ. Syst. (ICECS), Athens, Greece, pp. 768–771, Dec., 2010.

[2] B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.

[3] International Technology Roadmap for Semiconductors (ITRS), 2011 Edition [Online]. Available:

[4] B. R. Carlton, H. Lakdawala, E. Alpman, J. Rizk, Y. W. Li, B. Perez-Esparza, V. Rivera, C. F. Nieva, E. Gordon, P. Hackney, C.-H. Jan, I. A. Young, and K. Soumyanath, “A 32nm, 1.05V, BIST enabled, 10-40MHz, 11-9 bit, 0.13mm2 digitized integrator MASH ΔΣ ADC,” Symp. VLSI Circ. Digest of Technical Papers, Kyoto, Japan, pp. 36–37, June, 2011.

12 responses to “ADC research trends: CMOS node adoption

  1. George Storm

    I partly agree your verbal interpretation of the data.
    However, much of the apparent timing for averages appears to be due to (inevitable) truncation of data in 2011. The extended interest in popular nodes (e.g. 500nm/180nm) means that the average timing for subsequent less popular nodes is (relatively) early. So we will only be able to judge the extent of any acceleration once interest in the 65-nm node has definitively reduced.

    Regarding acceleration of first-papers: historically, initial fab structures on PDMs included only primitive devices; later, some digital cells were added, then DACs. More recently, there has been so much space that at-risk systems can be implemented on first silicon – hence the minimal delay to papers on ADCs. Therefore, the dates of “early adopter” ADC papers should henceforth be expected to track process development dates.

    I would also expect the delay between process introduction and first academic papers to have been reduced, as increased component count means that fabs can afford to make test sites available to preferred academic institutions. However, the delay to average must partly depend on the appearance of new technical issues as process shrinks. Nevertheless, although the introduction of SOI-FD at around the 0.28/0.2-um nodes is likely reduce the difficulty, it may in compensation extend the design life of the most popular – so any anomalous shorter delay will likely be confined to the next smaller node.

  2. The early adopter trend has been almost unchanged since the early adoption of 0.35 um. Do you suggest that the “abundance-of-space” effect started to kick in for ADCs already then?

    • George Storm

      Not quite – you will see the situation better if you can plot a graph of delay from process introduction to ADC paper. There will of course have been some variability from trend, which might make the exact line difficult to assess.
      So far as I can judge from the various graphs, the first “early adopter” paper was within two years of process introduction at 800nm (1989), and this has been the case at subsequent nodes.
      A same-year ADC paper was first seen at 65nm and then at 45nm. 32nm didn’t quite make it in the same year – but I think this was merely a matter of phasing. I imagine the delay from here on in will be somewhat under six months. (Naturally, this represents a slightly reduced slope from the 65-nm node onwards).
      N.B. apology – I mistyped in my previous posting: “0.28/0.2-um” should have read “28/20-nm”

      • Interesting thoughts.
        BTW, do you know of any source (preferably on-line and free) keeping some kind of “official” [or well-supported] back-trace of CMOS nodes and their year of introduction. From what I remember, the ITRS updates focus on the future projections, and does not provide the historical data.

        • George Storm

          It might be worth approaching foundries for various historic milestone dates (if available, first customer samples is probably the appropriate one). Otherwise you would need to rely on wikipedia or to search IEEE (probably conferences) for reports of logic or device measurements (these would give a related but different date). For printed papers, submission date is probably more meaningful than publication.
          (I don’t deliberately keep records of this, but my dates for 40nm downwards will not be not too bad. It could be worth asking for a steer via one of the LinkedIn groups or SemiWiki)

          • I’ll probably skip the foundries for now, and stick with Wikipedia, and possibly ask something on LinkedIn if I need more detail.
            Checking what digital ASICs came out on ISSCC every year would probably give a good idea if I subtract 1 from the ISSCC year.

  3. Regarding the timing of the averages (or mainstream), you’re entirely right: We can’t know for sure where the center of mass will end up for the more recent processes, since they are still active. Like I said in the post, it was only a highly subjective estimation based on the visual inspection of the available data.

    The data shown here was truncated to 2011 because if the available fraction of 2012 data should have been included, the contour plot would have given the false impression of all these nodes starting to decline – which at least not all of them are.

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