ADC performance evolution: Low-voltage operation – part 1


Figure 1. Two-dimensional view of CMOS scaling: Channel length and VDD.

EMBRACING LOW VOLTAGE OPERATION: As analog-to-digital converter implementations migrate to scaled-down CMOS technologies, they also face the inevitable downscaling of supply voltages (VDD), and hence signal swing [1]. A signal chain with a weak signal is more likely to suffer from noise than one with a strong signal. The scaling trends for VDD are therefore important as a background to the A/D-converter noise performance trends that will be treated in a few upcoming posts. There are also other reasons for a circuit designer to keep an eye on the evolution of supply voltage, such as the considerable challenges for high-gain OP-amp design or sampling linearity under low-voltage operation, so I hope you’ll find this post useful even on its own.

Voltage scaling: The stragglers, the mainstream, and the pioneers

Contrary to the minimum channel length (L), we can choose to go lower than the nominal supply voltage specified for a process. Possibly at our own risk, but at least it can be done. It has therefore been possible to scale VDD “ahead” of the node you actually use. Unless you have direct access to a semiconductor fab, you can’t do that with respect to L. This degree of freedom – at least for experimental ADC designs – has lead to the situation illustrated by Fig. 1:

  • Some (or as we shall see below, most) designs use the nominal supply voltage recommended for any given CMOS node.
  • Others may use the same node, but the design is not “fully scaled”. It relies on higher-than-nominal VDD, and possibly optional process steps that effectively recreate older and less scaled device technology as well.
  • A third category not only embraces the full scaling, but actually use a more aggressive scaling of supply voltages. These are the low-voltage pioneers.

This post will observe how supply voltage distribute over CMOS node for scientifically reported ADCs, and attempt to extract evolution trends and trajectories for VDD vs. L.

ADC supply voltage vs. CMOS node

As pointed out in [2], the reported supply voltage can vary as much as one order of magnitude within the same node for scientific A/D-converters. This is illustrated by the scatter plot of {L, VDD} for the entire CMOS ADC data set in Fig. 2. The VDD used in the plot is the highest supply voltage applied to each ADC, and the evolution of low-voltage state-of-the-art over CMOS nodes has been highlighted. Wismar, et al., reported a 90 nm VCO-based ∆-∑ modulator implementation running at 0.2 V supply voltage (operational @ 0.18 V), which is the lowest VDD published to this date [3].

Note that Fig. 2 differs form a similar graph in [2] in that the graph here is based on two more years of empirical data, and the plot in [2] shows the lowest VDD applied to each design instead of the highest. Also, the trajectory for the de facto nominal supply voltage vs. CMOS node is overlaid in Fig. 2. It is not necessarily the “official” VDD, but instead it was derived from the supply used by the majority of designs reported for each node. For nearly all nodes, the choice was abundantly clear. In 65 and 90 nm, however, there were significant subsets of designs using 1 V instead of the 1.2 V that was used by the majority.

Starting at 1.2 µm, the ultra-low voltage state-of-the-art appears to have followed a distinct trend of evolving as approximately one fifth of the nominal VDD. Because of the slowdown in nominal VDD scaling, that trend still holds in relation to the 0.2 V reported by Wismar.

VDD vs. CMOS node (scatter plot)

Figure 2. Supply voltages used for scientific ADCs vs. CMOS node. The low-voltage state-of-the-art data points have been highlighted, and the nominal/majority VDD trajectory superimposed.

Although the scatter in Fig. 2 shows all reported combinations of {L, VDD}, it does not reveal the distribution across scientific ADC papers. This is done in Fig. 3, where color contours represent the number of papers falling into a certain two-dimensional histogram bin. The bins used in this plot have been selected manually in order to create a meaningful, yet readable plot, so that bin centers align with major nodes on the L axis, and the most frequently used or otherwise interesting values on the VDD-axis. Furthermore, a non-linear, truncated, ad hoc mapping of contour levels was applied to handle the steep peeks at certain bins while still retaining visibility of all non-zero bins. The contours thus yield a simplified view of the actual distribution, and cannot be used to derive the actual bin counts or exact distribution. For completeness, Fig. 4 shows the full distribution of all unique combinations of {L, VDD} reported for scientific ADC implementations until Q1-2012.

Figures 3 and 4 show that the vast majority of experimental ADCs reported in scientific papers use the nominal supply voltage for each CMOS node, even if there is a large spread of actual VDD values used in each node. The variation extends significantly below and above the nominal values. We can also observe that the scaling rate for nominal supply voltage with CMOS node appears to have leveled out after 130 nm. Projected VDD for future nodes are found in [1].

In part 2, we will look at the trends for VDD over time.

VDD vs. CMOS node (contour plot)

Figure 3. Distribution of supply voltage used for scientific ADCs vs. CMOS node. Color contours indicate density of publications. The low-voltage state-of-the-art data points are superimposed along with the nominal VDD trajectory.

Figure 4. Distribution of all unique combinations of VDD and L (node) reported for CMOS ADC implementations in scientific papers until Q1-2012. Bin grid is not to scale.

See also …

ADC research trends: CMOS node adoption

ADC research trends: Migration to CMOS

ADC performance evolution: Thermal noise

ADC performance evolution: Relative noise floor

ADC Survey Data

References

[1] International Technology Roadmap for Semiconductors (ITRS), 2011 Edition [Online]. Available: http://www.itrs.net

[2] B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.

[3] U. Wismar, D. Wisland, and P. Andreani, “A 0.2V 0.44µW 20 kHz analog to digital ∑∆ modulator with 57 fJ/conversion FoM”, Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Montreux, Switzerland, pp. 187-190, Sept., 2006.

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5 responses to “ADC performance evolution: Low-voltage operation – part 1

  1. Pingback: ADC performance evolution: Low-voltage operation – part 2 | Converter Passion

  2. Pingback: ADC performance evolution: Thermal noise | Converter Passion

  3. Pingback: ADC performance evolution: Relative noise floor | Converter Passion

  4. Pingback: ADC performance evolution: Linearity (SFDR) | Converter Passion

  5. Pingback: ADC performance evolution: Thermal figure-of-merit (FOM) | Converter Passion

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