JITTER TRENDS: Previously we observed the evolution of absolute thermal noise levels in ADCs. In this second post in a series of three, we will look at sampling time uncertainty, commonly referred to as jitter. The future evolution of A/D-converter jitter performance will have great impact on the development of advanced communications infrastructure, or any other application where you wish to sample at radio frequencies (RF) or beyond. A thorough assessment of past and present jitter evolution trends is therefore a highly valuable reference for system-level strategists, as it gives an indication of what kind of ADC performance to expect in the future.
Observation of ADC jitter trends
Sampling a single-tone input with frequency fin and rms sampling time uncertainty σt in an otherwise ideal system yields a jitter-defined SNR in dBc defined by (1).
An ADC where the circuit noise is dominated by sampling jitter has circuit signal-to-noise ratio SNRC ≈ SNRJ. See definition of SNRC in previous post. Observing the SNR achieved at a particular input frequency therefore leads to a worst-case estimate of sampling jitter, and looking at the SNRC vs. fin progress for the entire body of scientific Nyquist ADC data thus renders a conservative estimate of jitter performance evolution over time. Figure 1 shows the state-of-the-art envelopes for SNRC vs. fin at 1980, 1990, and 2000 compared to present day (~Q1 2012). By using SNRC instead of SNR, the ideal quantization noise component that would falsely add to the jitter estimate is removed. For data points where the effect of jitter has fully kicked in, this actually makes little difference. Since not all papers report performance at such high input frequencies, the use of SNRC instead of SNR still gives a better jitter estimation.
An SNRJ vs. fin jitter raster according to (1) has been included as a visual guide in Fig. 1 for jitter values of 0.01, 0.1, 1, and 10 ps. The state-of-the-art in 1980 is defined by only a few designs and therefore difficult to interpret. By 1990, a much larger number of attempts have been made, and the high-frequency roll-off is almost perfectly aligned with the theoretical SNR limit for 8–10 ps jitter. Garuts et al. achieves 5.5 ps at 1 GHz input with a 4-b, 1 GS/s ADC (9.8 ps without quantization error subtraction) . During the following decade, the lowest jitter estimate was reduced by almost exactly ten times to the 0.53 ps reported by Singer et al. for an IF-sampling 12‑b, 65 MS/s ADC in . A slight slowdown is then observed for the last 11 years, when the jitter evolution front progress by less than a factor of ten across most of the frequency range. Current state-of-the-art is defined by the 14‑b, 125 MS/s, RF/IF-sampling ADC reported by Ali . The 88 fs rms jitter estimated at 500 MHz fin is a six times improvement over . Looking at Fig. 1, it is evident where the main effort was focused. Whereas the state-of-the-art boundary is almost straight at 1990, there is an obvious “bump” in the 50–200 MHz range by 2000, which has migrated to 100–500 MHz to this date, and a secondary bump has emerged recently at 1–2GHz, defined by data reported in . Although there are other applications matching these frequency ranges, the progress of the evolution front aligns very well with the evolution of requirements for wideband communications infrastructure. The current state-of-the art boundary is largely defined by publications stating wireless or digital communication as the target application. Hence it is concluded that communications applications have been a main driver for jitter performance over the last two decades. A point of concern for the communications industry could be that the current state-of-the-art  was achieved in 2005, using a 0.35 µm BiCMOS process. Observing the state-of-the-art estimate of σt (at any fin) over time, as shown in Fig. 2, jitter performance appears to be in a state of saturation. A closer inspection of the underlying data set gives further reason to assume saturation of jitter performance: Figure 3 shows the evolution of jitter performance vs. technology scaling. Although it’s possible that jitter eventually starts to improve in deeply scaled nodes, the current trend clearly supports the assumption of jitter performance saturation.
In the third and, for this time, final post on noise performance evolution, we will study the evolution of A/D-converter relative noise floor.
- Note that jitter was analyzed by observing Nyquist ADCs. Bandpass delta-sigma modulators can achieve much better combinations of SNR and input frequency. The current state-of-the-art is a continuous-time bandpass delta-sigma modulator by Luh . A significant part of the sampling jitter in a delta-sigma modulator is suppressed either by the noise transfer function or when selecting a band-of-interest in the subsequent signal processing. An arbitrarily small jitter estimate could be achieved simply by choosing to measure the SNR over a lower bandwidth. Delta-sigma, and other narrowband ADCs were therefore excluded from the jitter observation, but are included in both the previous and the upcoming noise-evolution posts.
- Designs that could influence the state-of-the-art envelope, but possibly suffered from numerical problems in the SNRC estimation (for reasons described in part 1), were handled as follows: (a) All data points for which N–ENOB < 0.05 were filtered out before generating Fig. 1, and (b) The design by van Valburg  was left outside the main estimation of state-of-the-art envelope in Fig. 2. No special handling was necessary for Fig. 3.
- ADCs using some form of optical or optoelectronic solution may be able to sample with considerably lower timing uncertainty. As of yet, such ADCs are quite rare, and mostly implemented in unusual or purely experimental technology. Optoelectronic or all-optical solutions may very well be the way forward if classic electronic sampling saturates at unacceptable jitter levels. The survey here, however, did not cover optically sampled A/D-converters.
See also …
- V. E. Garuts, E. O. Traa, Y.-C. S. Yu, and T. Yamaguchi, “A dual 4-bit, 1.5 Gs/s analog to digital converter,” IEEE Bipolar Circuits and Technology Meeting, pp. 141–145, Sept., 1988.
- L. Singer, S. Ho, M. Timko, and D. Kelly, “A 12b 65MSample/s CMOS ADC with 82dB SFDR at 120MHz,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 38–39, Feb., 2000.
- A. M. A. Ali, C. Dillon, R. Sneed, A. Morgan, J. Kornblum, L. Wu, and S. Bardsley, “A 14-bit 125 MS/s IF/RF sampling pipelined A/D converter,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, USA, pp. 391–394, Sept., 2005.
- C.-Y. Chen, J. Wu, J.-J. Hung, T. Li, W. Liu, and W.-T. Shih, “A 12-Bit 3 GS/s Pipeline ADC With 0.4 mm2 and 500 mW in 40 nm Digital CMOS,” IEEE J. Solid-State Circuits, Vol. 47, pp. 1013–1021, Apr., 2012.
- L. Luh, J. F. Jensen, C.-M. Lin, C.-T. Tsen, D. Le, A. E. Cosand, S. Thomas, and C. Fields, “A 4GHz 4th-order passive LC bandpass delta-sigma modulator with IF at 1.4GHz,” Symp. VLSI Circ. Digest of Technical Papers, Honolulu, USA, pp. 168–169, June, 2006, IEEE.
- J. van Valburg, and R. J. van de Plassche, “An 8-b 650-MHz Folding ADC,” IEEE J. Solid-State Circuits, Vol. 27, pp. 1662-1666, Dec., 1992.