ADC performance evolution: Linearity (SFDR)

SFDR-vs-fin evolution

Figure 1. Evolution of SFDR-vs.-fin envelope for scientifically reported ADCs: Current state-of-the art is compared to state-of-the-art envelopes at 1990 (#) and 2000 (<).

LINEARITY TRENDS: After observing trends for technology scaling, voltage scaling, and noise, we have arrived at linearity. As far as the blogger is aware, there has been no large survey on A/D-converter linearity evolution published to this date, except for a recent work by Walden [1], where an “SFDR-bits” vs. fin scatter plot illustrates the state-of-the-art movement between 1999 and 2007 for the outermost corner/edge of the data, based on approximately 175 ADCs. In this post we will instead observe the migration of the entire envelope (state-of-the-art) for SFDR vs. input frequency (and sampling rate) in order to observe how SFDR evolved across multiple frequency ranges between 1990, 2000 and present (~Q1-2012). We will also slice through the data set, and specifically observe SFDR evolution at four very different speed grades of minimum sampling rate. The underlying data is from a survey of 1708 scientific ADC papers published between 1974 and Q1-2012.

ADC linearity trends: SFDR-vs-frequency envelope

While SNR, or an aggregate noise-and-distortion measure such as SNDR, is a sufficient measure of ADC performance for some applications, there are other applications where non-linear distortion is independently specified. Such applications include high-end audio and many wireless communication systems. Wireless communication systems often need to cope with the presence of a strong interferer in the form of a neighboring channel or carrier, while correctly interpreting a weak signal of interest. Without a sufficiently linear signal path, the interfering signal will generate harmonics or intermodulation products that may completely block the in-channel signal. The evolution of ADC linearity is therefore as important as the noise and ENOB evolution.

State-of-the-art envelopes for single-tone spurious-free dynamic range (SFDR) vs. input frequency fin and Nyquist sampling rate fs have been plotted in Fig. 1 and Fig. 2 respectively. Current state-of-the-art at ~Q1-2012 is compared to that of 1990 and 2000 in order to illustrate the evolution over all frequencies. Starting with the envelopes at 1990, the linearity vs. fin and fs is evenly distributed across almost straight lines representing the increasing difficulty to achieve high linearity as the input frequency and sampling rate is increased. The first of the two noticeable performance peaks in Fig. 1 coincide with the 20 kHz audio bandwidth, and the second peak is defined by video and instrumentation ADCs in the frequency range 10-100 MHz. It is evident from both plots that most of the progress from 1990 to the current state-of-the-art was achieved in the first decade 1990-2000 when SFDR vs. fin was improved by 20-40 dB across all input frequencies in the 100 kHz to 1GHz range, and SFDR vs. fs increased by 5-30 dB for the same range of sampling frequencies. Although state-of-the-art linearity has been increased by 5-10 dB over many segments of the frequency range during the last 11 years, Figs. 1 and 2 clearly shows that there has been a slowdown in the evolution of linearity over a broad range of frequencies and speed grades. One noticeable exception is the 30 dB performance lift in the 100-250 MS/s speed range, which reflects the specifications of the more recent wideband radio base-stations (RBS). It was concluded in a previous post that the evolution of communications standard requirements has been a strong driver for ADC jitter performance. Observing that the strongest push of the linearity envelopes also occurred at frequencies and sampling rates matching the specifications for wideband RBS, e.g., [2]-[5], it is concluded that communications applications have been a key driver for ADC linearity as well. This is also the conclusion of Walden in [1]. Another significant achievement during the last decade has been to improve performance at the high-frequency end of the spectrum, with sampling rates above 4 GS/s and input frequencies beyond 1 GHz [6]-[14]. Again, a similar observation is made in [1].

SFDR-vs-fs evolution

Figure 2. Evolution of SFDR-vs.-fs envelope for scientifically reported ADCs: Current state-of-the art is compared to state-of-the-art envelopes at 1990 (#) and 2000 (<).

ADC linearity trends: SFDR by speed grade

Figure 3 shows the evolution of peak SFDR at minimum speed grades of fs ≥ {10k, 1M, 100M, 1G} samples/s. The curves show the monotonically improving upper edge for each subset of survey data. What is included in each subset is defined by the four minimum sampling rate constraints. As in Fig. 1 and Fig. 2, the overall scatter is removed for readability.

My interpretation of Fig. 3 is as follows:

  • 1MS/s ADCs appear to have saturated at an SFDR of 108 dB [15], and have not improved since 1996.
  • 100 MS/s ADCs has slowed-down evolution beyond 100 dB to ~6 dB/decade or less. Current state-of-the-art is 102 dB SFDR [5].
  • At very low, and very high sampling rates there are no signs of saturation yet. For ADCs with fs ≥ 10 kS/s, there has been an almost constant progress of ~9dB/decade from 1992 [16] to 2009 [17].
  • ADCs with fs ≥ 1 GS/s are currently evolving at an accelerated rate of ~3 dB/year. If this rate is maintained, gigasample ADCs could go from 75 dB [18] to upwards of 100 dB SFDR by 2020.
  • The accelerated rate of evolution seen at different times for different speed grades may reflect how research activities migrate to higher and higher sampling rates depending on what applications are in focus. Previously more of a niche product, gigasample ADCs are now becoming a mainstream necessity.
SFDR evolution by speed grades

Figure 3. Scientifically reported ADC implementations: Peak SFDR evolution over time for minimum sampling rates of 10k (o), 1M (#), 100M (<), and 1GS/s (diamond).

Commercial ADC parts

Although not shown here, the results were also compared with the data from 595 commercially released ADC parts. Current state-of-the-art envelope for both sets align well across most of the speed range, with one significant exception: There are already commercial parts with significantly better SFDR than their scientific counterparts at 2 MSPS and below, e.g., AD7766 [19] and AD7986 [20]. Commercial ADCs appear to have evolved beyond their experimental siblings in later years within this speed segment(*).

Another difference is in the paths each subset has followed towards today’s (mostly similar) state-of-the-art. In the GSPS range there is for example MAX 104 [21], specifying 69 dB SFDR at fin = 125 MHz almost a decade before the scientific publication by Taft [22], while scientific efforts seem to have been ahead in other frequency ranges (e.g., below 2MS/s) during earlier years(*).

Linearity trends are therefore more difficult to interpret, and to some degree depend on what products were reported scientifically and not. Such dependency could not be observed for any noise-related parameter analyzed in this series of posts.

(*) Please note that these are only my best guesstimates, as the commercial data set (although large) is not as exhaustive as that for scientific ADCs.

In the next post I plan to review the simultaneous evolution of {ENOB, fs}. Subscribe to the blog, and you won’t miss it.

See also …

ADC performance evolution: Thermal noise

ADC performance evolution: Jitter

ADC performance evolution: Relative noise floor

ADC performance evolution: Low-voltage operation – part 1

ADC performance evolution: Low-voltage operation – part 2

ADC survey data


  1. R. Walden, “Analog-to-digital conversion in the early twenty-first century,” Wiley Encyclopedia of Computer Science and Engineering, pp. 126–138, Wiley, 2008.
  2. A. Namdar, and B. H. Leung, “A 400MHz 12b 18mW IF digitizer with mixer inside a ΣΔ modulator loop,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 62–63, Feb., 1999.
  3. A. M. A. Ali, C. Dillon, R. Sneed, A. S. Morgan, S. Bardsley, J. Kornblum, and L. Wu, “A 14-bit 125 MS/s IF/RF sampling pipelined ADC with 100 dB SFDR and 50 fs jitter,” IEEE J. Solid-State Circuits, Vol. 41, pp. 1846–1855, Aug, 2006.
  4. A. M. A. Ali, A. Morgan, C. Dillon, G. Patterson, S. Puckett, P. Bhorashkar, H. Dinc, M. Hensley, R. Stop, S. Bardsley, D. Lattimore, J. Bray, C. Speir, and R. Sneed, “A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration,” IEEE J. Solid-State Circuits, Vol. 45, pp. 2602-2612, Dec., 2010.
  5. R. Payne, M. Corsi, D. Smith, T.-L. Hsieh, and S. Kaylor, “A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC With 100 dBFS SFDR,” IEEE J. Solid-State Circuits, Vol. 45, pp. 2613-2622, Dec., 2010.
  6. K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernilo, C. Tan, and A. Montijo, “A 20GS/s 8b ADC with a 1MB memory in 0.18μm CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 318–319, Feb., 2003.
  7. W. Cheng, W. Ali, M.-J. Choi, K. Liu, T. Tat, D. Devendorf, L. Linder, and R. Stevens, “A 3b 40GS/s ADC-DAC in 0.12μm SiGe,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 262–263, Feb., 2004.
  8. L. Y. Nathawad, R. Urata, B. A. Wooley, and D. A. B. Miller, “A 20GHz bandwidth, 4b photoconductive-sampling time-interleaved CMOS ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 320–321, Feb., 2003.
  9. S. M. Louwsma, A. J. M. van Tuijl, M. Vertregt, and B. Nauta, “A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS,” IEEE J. Solid-State Circuits, Vol. 43, pp. 778–786, Apr., 2008.
  10. B. Chan, B. Oyama, C. Monier, and A. Guiterrez-Aiken, “An ultra-wideband 7-Bit 5-Gsps ADC implemented in submicron InP HBT technology,” IEEE J. Solid-State Circuits, Vol. 43, pp. 2187–2193, Oct., 2008.
  11. P. Schvan, J. Bach, C. Falt, P. Flemke, R. Gibbins, Y. Greshischev, N. Ben-Hamida, D. Pollex, J. Sitch, S.-C. Wang, and J. Woczanski, “A 24GS/s 6b ADC in 90nm CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 544–545, Feb., 2008.
  12. S. Shahramian, S. P. Voinigescu, and A. C. Carusone, “A 35-GS/s, 4-bit flash ADC with active data and clock distribution trees,” IEEE J. Solid-State Circuits, Vol. 44, pp. 1709–1720, June, 2009.
  13. J. Ryckaert, A. Geis, L. Bos, G. Vand Der Plas, and J. Craninckx, “A 6.1 GS/s 52.8 mW 43 dB DR 80 MHz Bandwidth 2.4 GHz RF Bandpass ∆∑ ADC in 40 nm CMOS,” Proc. of IEEE Radio Frequency Integrated Circ. Symp., Anaheim, CA, USA, pp. 443-446, May, 2010.
  14. Y. M. Greshishchev, J. Aguirre, M. Besson, R. Gibbins, C. Falt, P. Flemke, N. Ben-Hamida, D. Pollex, P. Schvan, and S.-C. Wang, “A 40GS/s 6b ADC in 65nm CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 390–391, Feb., 2010.
  15. M. K. Mayes, and S. W. Chin, “A 200 mW, 1 Msample/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller,” IEEE J. Solid-State Circuits, Vol. 31, pp. 1862-1872, Dec., 1996.
  16. R. J. van de Plassche, and H. J. Schouwenaars, “A monolithic 14 bit A/D converter,” IEEE J. Solid-State Circuits, Vol. SC-17, pp. 1112-1117, Dec., 1982.
  17. J.-Y. Wu, Z. Zhang, R. Subramoniam, and F. Maloberti, “A 107.4 dB SNR multi-bit sigma delta ADC with 1-ppm THD at 0.12 dB from full scale input,” IEEE J. Solid-State Circuits, Vol. 44, pp. 3060-3066, Nov., 2009.
  18. R. Payne, C. Sestok, W. Bright, M. El-Chammas, M. Corsi, D. Smith, and N. Tal, “A 12b 1GS/s SiGe BiCMOS Two-Way Time-Interleaved Pipeline ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, USA, pp. 182-184, Feb., 2011.
  19. AD7766, “24-Bit, 8.5 mW, 109 dB, 128 kSPS/64 kSPS/32 kSPS ADCs” Data Sheet, Analog Devices Inc., Aug, 2007.
  20. AD7986, “18-Bit, 2 MSPS PulSAR 15 mW ADC in LFCSP (QFN),” Data Sheet, Analog Devices Inc., Apr., 2009.
  21. MAX104, “+/-5V, 1Gsps, 8-bit ADC with on-chip 2.2GHz track/hold amplifier,” Data Sheet, Maxim Integrated Products Inc., Sept., 1999.
  22. R. C. Taft, P. A. Francese, M. R. Tursi, O. Hidri, A. MacKenzie, T. Hoehn, P. Schmitz, H. Werker, and A. Glenny, “A 1.8V 1.0GS/s 10b self-calibrating unified-folding-interpolating ADC with 9.1 ENOB at Nyquist frequency,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 78-79, Feb., 2009.

3 responses to “ADC performance evolution: Linearity (SFDR)

  1. Pingback: ADC performance evolution: Relative noise floor | Converter Passion

  2. Pingback: ADC performance evolution: Sampling rate and resolution | Converter Passion

  3. Pingback: ADC performance evolution: Thermal figure-of-merit (FOM) | Converter Passion


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