ADC performance evolution: Sampling rate and resolution


ENOB-vs-fs evolution front

Figure 1. Evolution of ENOB vs. fs envelope for scientifically reported ADCs. Current state-of-the art is compared to state-of-the-art envelopes at 1990 (#) and 2000 (<). Theoretical limits for thermal noise @ VFS = 1V (dotted) and jitter (dashed) are indicated.

SPEED/RESOLUTION TRENDS: Previous posts analyzed noise and linearity separately. Another common approach is to review the overall ADC performance in terms of sampling rate and effective resolution ENOB. In Fig. 1, the current state-of-the-art at ~Q1-2012 is compared to the envelopes for 1990 and 2000 in order to show the simultaneous evolution of the two parameters throughout the entire parameter space. SNR-only results have been excluded from this plot because ENOB is not fully defined by SNR. Hence, there is no experimental data available before 1980. By 1990 the curve has assumed the expected shape. Between 1990 and 2000 there is a 1-4 bits improvement across the full range of sampling rates. The main advances were in the 200kS/s – 100MS/s speed range. This corresponds to typical telecommunications specifications – from single-carrier GSM to multi-carrier WCDMA receivers. From year 2000 to present day, the more significant advances were at 12.5 MS/s [1], from 100–250 MS/s, [2]-[3], at 3 GS/s [4], and above 10 GS/s [5]-[7].

The thermal noise limits according to equation (4) in the thermal noise post have been included as a visual guide, using VFS = 1V, = 300 K, and Rn = {50, 2000} Ω. Similarly, the theoretical jitter-limited ENOB at fin fs/2 according to equation (1) in the jitter post has been added for σt = {0.1, 1, 10} ps. The Rn and σt values were deliberately chosen to simplify comparison with a similar plot in Walden’s survey [8] (see also Additional remarks below). Although the jitter limits should preferably be observed from SNR vs. fin (as done in the post on jitter trends), the shape of the state-of-the-art envelopes in Fig. 1 clearly indicate the regions where ADC performance is limited by thermal noise and jitter respectively. The design by Naiknaware et al. [10] is limited by thermal noise, while those by Poulton et al. [5] and Greshishchev et al. [7] are limited by sampling jitter (and/or metastability [9]). At the boundary between thermal noise and jitter limited designs are the ADCs that suffer from both noise sources in equal amount, such as the design by Ali et al. [3]. Designs in this corner put strict demands on the simultaneous design for jitter and thermal noise.

In the next post will take a look at the trends for ADC FOM.

Additional remarks

  • It may seem that the state-of-the-art thermal noise according to Fig. 1 is equivalent to less than 2 kΩ for some designs. This would obviously be in contradiction to the 2.5 and 6.2 kΩ state-of-the-art reported for delta-sigma modulator and Nyquist ADCs, respectively. The thermal noise limits in Fig. 1 are only valid for VFS = 1 Vpp, and the apparently better results here are because of a larger full-scale range, e.g., 2.5 V for [3]. The correct noise-resistance estimations are found here.
  • The corresponding jitter limits in [8] have a 0.5-bit offset because it appears that Walden derives the rms-signal to peak-noise ratio by assuming that the signal is always sampled where the slope is greatest, i.e., in the zero-crossings [9]. In reality, the signal is sampled anywhere along the waveform for all but pathological cases, and therefore the rms slope should be used instead, as was done in this treatment.
  • In [11], the evolution trends for peak sampling rate at fixed minimum ENOB grades {4, 8, 12, 14} bits, and the complementary peak ENOB at fixed minimum sampling rates {10k, 100k, 1M, 100M, 1G} S/s are shown in a style similar to Fig. 3 in the previous post.

See also …

ADC performance evolution: Linearity (SFDR)

ADC performance evolution: Thermal noise

ADC performance evolution: Jitter

ADC performance evolution: Relative noise floor

ADC survey data

References

  1. C. P. Hurrell, C. Lyden, D. Laing, D. Hummerston, and M. Vickery, “An 18 b 12.5 MS/s ADC With 93 dB SNR,” IEEE J. Solid-State Circuits, Vol. 45, pp. 2647–2654, Dec., 2010.
  2. S. Devarajan, L. Singer, D. Kelly, S. Decker, A. Kamath, and P. Wilkins, “A 16b 125MS/s 385mW 78.7dB SNR CMOS pipeline ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 86–87, Feb., 2009.
  3. A. M. A. Ali, A. Morgan, C. Dillon, G. Patterson, S. Puckett, P. Bhorashkar, H. Dinc, M. Hensley, R. Stop, S. Bardsley, D. Lattimore, J. Bray, C. Speir, and R. Sneed, “A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration,” IEEE J. Solid-State Circuits, Vol. 45, pp. 2602-2612, Dec., 2010.
  4. C.-Y. Chen, and  J. Wu, “A 12b 3GS/s Pipeline ADC with 500mW and 0.4 mm2 in 40nm Digital CMOS,” Symp. VLSI Circ. Digest of Technical Papers, Kyoto, Japan, pp. 120–121, June, 2011.
  5. K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernilo, C. Tan, and A. Montijo, “A 20GS/s 8b ADC with a 1MB memory in 0.18μm CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 318–319, Feb., 2003.
  6. S. Shahramian, S. P. Voinigescu, and A. C. Carusone, “A 35-GS/s, 4-bit flash ADC with active data and clock distribution trees,” IEEE J. Solid-State Circuits, Vol. 44, pp. 1709–1720, June, 2009.
  7. Y. M. Greshishchev, J. Aguirre, M. Besson, R. Gibbins, C. Falt, P. Flemke, N. Ben-Hamida, D. Pollex, P. Schvan, and S.-C. Wang, “A 40GS/s 6b ADC in 65nm CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 390–391, Feb., 2010.
  8. R. Walden, “Analog-to-digital conversion in the early twenty-first century,” Wiley Encyclopedia of Computer Science and Engineering, pp. 126–138, Wiley, 2008.
  9. R. H. Walden, “Analog-to-digital converter survey and analysis,” IEEE J. Selected Areas in Communications, no. 4, pp. 539–550, Apr. 1999.
  10. R. Naiknaware, and T. Fiez, “142dB ∆∑ ADC with a 100nV LSB in a 3V CMOS process,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), Orlando, USA, pp. 5–8, May, 2000
  11. B. E. Jonsson, “A survey of A/D-converter performance evolution,” Proc. of IEEE Int. Conf. Electronics Circ. Syst. (ICECS), Athens, Greece, pp. 768–771, Dec., 2010.
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5 responses to “ADC performance evolution: Sampling rate and resolution

  1. Pingback: ADC performance evolution: Linearity (SFDR) | Converter Passion

  2. Pingback: ADC performance evolution: Thermal noise | Converter Passion

  3. Pingback: ADC performance evolution: Thermal figure-of-merit (FOM) | Converter Passion

  4. Hello – Thank you for this website. As a person who is not very familiar with ADCs, I enjoyed the useful information you provided here, and I appreciate your effort and passion.
    I have a question regarding ADCs that I think you probably know the answer. Is there any fundamental limit for the performance of an ADC? I mean, any resolution, FOM, or … that we are sure the ADCs, even in the future, will never do better than that?

    • Important question, indeed.
      Most of what I shared so far has focused on what I call “pragmatic” limits. Limits that could possibly be pushed by burning more power, using parallelism, averaging or some other brute force approach — but according to present observations no one did that anyway. Perhaps because the implementation would be so ridiculously bulky, power hungry or expensive that it would be embarrassing to publish or market it. Or something like that.
      A limit that sounds pretty hard is Heisenberg’s principle of uncertainty which was proposed as an outer limit to sampling accuracy by Walden in [9] and [8] above. I haven’t considered that limit very much, but you could check his paper(s) if you did not already.
      Generally, thermal noise is a real pain, so thats where we might find other hard limits. For sure, that’s where the majority of pragmatic limits I’ve shown originate from.
      /Bengt

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