**POWER EFFICIENCY TRENDS**: A series of blog posts on A/D-converter performance trends would not be complete without an analysis of

*figure-of-merit*(FOM) trends, would it? We will therefore take a look at the two most commonly used FOM, starting with the by far most popular:

where *P* is the *power dissipation*, *f _{s}* is Nyquist

*sampling rate*, and ENOB is the

*effective number of bits*defined by the

*signal-to-noise and-distortion ratio*(SNDR) as:

*F*_{A1} is sometimes referred to as the *Walden* or ISSCC FOM and relates the ADC power dissipation to its performance, represented by sampling rate and conversion error *amplitude*. The best reported *F*_{A1} value each year has been plotted for *delta-sigma modulators* (DSM) and Nyquist ADCs in Fig. 1. Trajectories for state-of-the-art have been indicated, and trends have been fitted to these state-of-the-art data points. The average improvement trend for *all* ADCs (**2×/2.6 years**) is included for comparison.

By dividing the data into DSM and Nyquist subsets, it is seen that delta-sigma modulators have improved their state-of-the-art FOM at an almost constant rate of **2 ×/2.5 years** throughout the existence of the field – just slightly faster than the overall average. State-of-the-art Nyquist ADCs have followed a steeper and more S-shaped evolution path. Their overall trend fits to a

**2**, although it is obvious that evolution rates have changed significantly over time. A more accurate analysis of Nyquist ADC trends should probably make individual fits of the early days glory, the intermediate slowdown, and the recent acceleration phase. This was done in [1] where evolution was analyzed with DSM and Nyquist data merged. However, for simplicity I’ll just stick to the more conservative overall Nyquist trend. [I wouldn’t want anyone to suggest that I’m producing “

**×**improvement every 1.8 years*subjective*” or “

*highly speculative*” trend estimates, would I? 😉 ]

Still, if anyone *is* curious to know … 🙂 … the state-of-the-art data points fit to a **2×/14 months** trend between 2000 and 2010. That’s actually ** faster than Moore’s Law**, which is traditionally attributed a 2

**×/**18 months rate [2]-[3]. A new twist on “

*More than Moore*”, perhaps? Even the more conservative overall 2

**×**/21 months trend is close enough to conclude that the state-of-the-art FOM for Nyquist ADCs has developed exponentially in a fashion closely resembling Moore’s Law. And that’s

*got*to be an impressive trend for any analog/mixed circuit performance parameter.

Irrespective of what’s the best fit to data, it should be evident from Fig. 1 that Nyquist ADCs broke away from the overall trend around year 2000, and has since followed a steeper descent in their figures-of-merit. They have also reached further (**4.4 fJ**) [4] than DSM (**35.6 fJ**) [5]. The overall trend projects to a **0.2 fJ **ADC FOM in** 2020**. Whether or not that’s possible, we’ll leave for another post. A deeper look at the data also reveals that:

- The acceleration in state-of-the-art is almost completely defined by
*successive-approximation*(SAR) ADCs [4], [6]-[11], accompanied by a single*cyclic*ADC [12]. The superior energy efficiency of the SAR architecture was empirically shown in [13]. - A significant part of the acceleration can be explained by the increased tendency to leave out, for example I/O power dissipation when reporting experimental results – a trend also observed by
*Bult*[14]. The FOM in the graph was intentionally calculated from the*on-chip*rather than*total*power dissipation because: (a) ADCs are increasingly used as a system-on-chip (SoC) building block, which makes the stand-alone I/O power for a prototype irrelevant, and (b) Many authors don’t even report the I/O power anymore. *F*_{A1}has a bias towards low-power, medium resolution designs rather than high-resolution, and thus benefits from CMOS technology scaling as shown in [15],[16]. An analysis of the underlying data shows that, for the best*F*_{A1}every year, the trajectories for ENOB and*P*follows distinct paths towards consistently lower power and medium resolution. You simply gain more in*F*_{A1}by lowering power dissipation than by increasing resolution because (1) does not correctly describe the empirically observed power-resolution tradeoff for ADCs [13],[15].

In order to compare high-resolution ADCs limited by thermal noise, it has therefore been proposed to use a slightly different FOM, sometimes labeled the “*Thermal FOM*” [17]-[18],

This figure-of-merit will be the topic of the next post.

#### See also …

Walden’s survey [19]

#### References

- B. E. Jonsson, “A survey of A/D-converter performance evolution,”
*Proc. of IEEE Int. Conf. Electronics Circ. Syst. (ICECS)*, Athens, Greece, pp. 768–771, Dec., 2010. - G.E. Moore, “Cramming more components onto integrated circuits,”
*Electronics*, Vol. 38, No. 8, Apr. 1965. - G. E. Moore, “No exponential is forever: but “forever” can be delayed!,” IEEE
*ISSCC, Dig. Tech. Papers*, San Francisco, CA, Feb. 2003, pp. 20–23. - M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC,”
*Proc. of IEEE Solid-State Circ. Conf. (ISSCC)*, San Francisco, California, pp. 244–245, Feb., 2008. - J. Xu, X. Wu, M. Zhao, R. Fan, H. Wang, X. Ma, and B. Liu, “Ultra Low-FOM High-Precision ΔΣ Modulators with Fully-Clocked SO and Zero Static Power Quantizers,”
*Proc. of IEEE Custom Integrated Circ. Conf. (CICC)*, San Jose, California, USA, pp. 1–4, Sept., 2011. - A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS,”
*IEEE J. Solid-State Circuits*, Vol. 47, pp. 1022–1030, Apr., 2012. - T.-C. Lu, L.-D. Van, C.-S. Lin, C.-M. Huang, “A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/Conversion-Step SAR ADC for Biomedical Applications,”
*Proc. of IEEE Custom Integrated Circ. Conf. (CICC)*, San Jose, California, USA, pp. 1–4, Sept., 2011. - S.-K. Lee, S.-J. Park, Y. Suh, H.-J. Park, and J.-Y. Sim, “A 1.3µW 0.6V 8.7-ENOB Successive Approximation ADC in a 0.18µm CMOS,”
*Symp. VLSI Circ. Digest of Technical Papers*, Honolulu, USA, pp. 242–243, June, 2009. - H.-C. Hong, and G.-M. Lee, “A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC,”
*IEEE J. Solid-State Circuits*, Vol. 42, pp. 2161–2168, Oct., 2007. - M. D. Scott, B. E. Boser, and K. S. J. Pister, “An Ultra-Low Power ADC for Distributed Sensor Networks,”
*Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC)*, Firenze, Italy, pp. 255–258, Sept., 2002. - M. D. Scott, B. E. Boser, and K. S. J. Pister, “An Ultralow-Energy ADC for Smart Dust,”
*IEEE J. Solid-State Circuits*, Vol. 38, pp. 1123–1129, July, 2003. - D. Muthers, and R. Tiekert, “A 0.11mm2 low-power A/D-converter cell for 10b 10MS/s operation,”
*Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC)*, Leuven, Belgium, pp. 251–254, Sept., 2004. - B. E. Jonsson, “An empirical approach to finding energy efficient ADC architectures,”
*Proc. of 2011 IMEKO IWADC & IEEE ADC Forum*, Orvieto, Italy, pp. 1–6, June 2011. [PDF @ IMEKO] - K. Bult, “Embedded analog-to-digital converters,”
*Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC)*, Athens, Greece, pp. 52–60, Sept., 2009. - B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,”
*Proc. of 2011 IMEKO IWADC & IEEE ADC Forum*, Orvieto, Italy, pp. 1–6, June 2011. [PDF @ IMEKO] - B. E. Jonsson, “On CMOS scaling and A/D-converter performance,”
*Proc. of NORCHIP*, Tampere, Finland, Nov. 2010. - A. M. A. Ali, C. Dillon, R. Sneed, A. S. Morgan, S. Bardsley, J. Kornblum, and L. Wu, “A 14-bit 125 MS/s IF/RF sampling pipelined ADC with 100 dB SFDR and 50 fs jitter,”
*IEEE J. Solid-State Circuits*, Vol. 41, pp. 1846–1855, Aug, 2006. - C. Wulff, and T. Ytterdal, “Design of a 7-bit, 200MS/s, 2mW pipelined ADC with switched open-loop amplifiers in a 65nm CMOS technology,”
*Proc. of NORCHIP*, Aalborg, Denmark, Nov., 2007. - R. Walden, “Analog-to-digital conversion in the early twenty-first century,”
*Wiley Encyclopedia of Computer Science and Engineering*, pp. 126–138, Wiley, 2008.