ADC Survey: Christmas 2012 update on FOM


ADC FOM UPDATE: I’ve understood that many Converter Passion readers are the very scientists who advance the state-of-the-art for A/D-converters. You are most certainly keeping a close eye on the progress yourselves. But in case you haven’t had time to scan the output of every major conference and top journal lately, this post will summarize the figure-of-merit (FOM) evolution since the Spring 2012 Update.

What’s new?

This update adds coverage for the 2012 versions of Symposium on VLSI Circuits, ESSCIRC and CICC. Also the most recent issues of IEEE Journal of Solid-State Circuits (JSSC), and Transactions on Circuits and Systems pt. I and II. A total of 64 new sources were added to the survey, so that it now includes 3917 experimental data points extracted from 1772 scientific papers published between 1974 and Oct/Dec 2012.

ISSCC/Walden FOM

As mentioned in the previous update, the 4.4 fJ reported by van Elzakker et al. at ISSCC 2008 [1] has been an impressively persistent world record for “The FOM”

F_{A1} = \dfrac{P}{{2}^{ENOB}\times f_{s}}

It lasted for over four years until June 2012 until Tai et al [2] presented a 3.2 fJ SAR ADC at the IEEE Symposium for VLSI Circuits. Congratulations to the team from National Taiwan University, Taipei, Taiwan for their outstanding achievement. With their 0.35 V design, the NTU team were the new FOM champions between June and August 2012.

In September there was ESSCIRC. This year’s ESSCIRC had no less than four ADCs with a sub-10 fJ FOM [3]-[6]. No extra points for guessing the architecture – yes, they are all SAR. Among the four, the 2.8 fJ, 0.7 V, 7–10-b, flexible SAR by Harpe, et al. [3], is the new winner. The Eindhoven-based team behind the impressive world-record FOM are from the Holst Centre and Eindhoven University of Technology, The Netherlands. Excellent job, indeed! Many greetings from Converter Passion.

Beside the winners, all designs that achieved an FA1 < 10 fJ since the last update are listed below. Their combinations of {FA1, fs, ENOB, technology, VDDmax} are shown. In addition to all being variations of the SAR architecture, they are also close to the 9-b sweet spot for FA1, as predicted in “The path to a good A/D-converter FOM” and [7]. Except for the 7.07-b design by Yoshioka, et al. [6], they are all gathered within a 0.5-b slim interval centered just above 9-b. As explained in [7], this is not by accident.

Another clear trend is to operate the ADC at a lower-than-nominal supply voltage. As you can se from the table, the CMOS nodes range from 180 to 45 nm, but all six are run at low or ultra-low voltage. This is directly beneficial as it reduces the digital switching power. It is also likely to cause the converter to become limited by analog noise, which is pretty much a requirement when you’re aiming for energy-optimal operation.

FOM [fJ] Speed [S/s] ENOB Node [nm] VDD [V] 1st Author Ref
2.8 2M 9.31 90 0.7 Harpe [3]
3.2 100k 9.06 90 0.35 Tai [2]
3.9 2M 9.29 65 0.7 Yin [4]
4.5 1k 8.80 65 0.6 Zhang [5]
6.1 1.3M 7.07 45 0.4 Yoshioka [6]
8.0 200k 9.33 180 0.6 Huang [8]

What’s in the future?

It seems that a larger body of research efforts are now catching up with the rather extreme step taken by van Elzakker et al. The region below 10 fJ is rapidly becoming more densely populated. Within a six months period we saw two new world records, and with so much focus on this particular performance measure, we are likely to see more. In fact, judging from the titles in the ISSCC 2013 advance program, there are already two designs below 2.8 fJ lining up to be presented there. Perhaps more. Wish I could go there too.

Historically, the state-of-the-art FOM has mainly been reported in JSSC and at ISSCC, with the occasional publication at other conferences. As noted above, we can expect more to come out of ISSCC in the future, but ESSCIRC has clearly raised its profile with respect to ADC FOM in this millennium. Looking at the number of unique publications advancing the state-of-the-art FOM over time sorted by source publication, we get the “market share” of world records for each conference/journal, as shown in Fig. 1. Since the data between 2000 and 2012 consists of only 7 unique FOM advancements, we can’t be too sure about the trends. But it certainly makes ESSCIRC look good, doesn’t it?

Pie charts

Fig. 1. Where was the state-of-the-art FOM published? (a) Accumulated total (b) 1982–1999 (b) 2000–2012. [Click to enlarge]

Thermal FOM

As discussed in a previous post, the overall evolution of the “Thermal FOM”

F_{B1} = \dfrac{P}{{2}^{2\times ENOB}\times f_{s}}

over time has slowed down, and as explained in [9] it may not improve much over technology scaling. It is therefore no surprise that the overall FB1 remains unchanged at the 1.1 aJ reported by Xu [10].

Thermal FOM for Nyquist ADCs

New thermal-FOM champions for Nyquist converters are actually the same as the Walden-FOM winners above: First, the design by Tai et al. [2] nudged the previous 6.6 aJ record by Verbruggen et al. [11] down to 6.0 aJ. After a few months, Harpe et al. took the thermal FOM down to 4.4 aJ, which is the current world record.

Final words

All papers highlighted in this update represent considerable efforts and significant achievements with respect to energy efficiency. It was a joy reading them, and it will be exciting to see how far this evolution will take us.

To the blog readers that celebrate Christmas, I wish you a Merry one – to the rest, a Joyful Season. To all of us, a Happy New Year!

Next up is a book review, which I hope to post soon.

<- Previous FOM update

References

  1. M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.
  2. H.-Y. Tai, H.-W. Chen, and H.-S. Chen, “A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS,” Symp. VLSI Circ. Digest of Technical Papers, Honolulu, USA, pp. 92–93, June, 2012.
  3. P. Harpe, G. Dolmans, K. Philips, and H. de Groot, “A 0.7V 7-to-10bit 0-to-2MS/s Flexible SAR ADC for Ultra Low-Power Wireless Sensor Nodes,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Bordeaux, France, pp. 373–376, Sept., 2012.
  4. G. Yin, H.-G. Wei, U-F. Chio, S.-W. Sin, S.-P. U, Z. Wang, and R. P. Martins, “A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Bordeaux, France, pp. 377–380, Sept., 2012.
  5. D. Zhang, and A. Alvandpour, “A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Bordeaux, France, pp. 369–372, Sept., 2012.
  6. K. Yoshioka, A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with Wide Range Threshold Configuring Comparator,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Bordeaux, France, pp. 381–384, Sept., 2012.
  7. B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, June 2011. [PDF @ IMEKO]
  8. G.-Y. Huang, S.-J. Chang, C.-C. Liu, and Y.-Z. Lin, “A 1-μW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications,” IEEE J. Solid-State Circuits, Vol. 47, pp. 2783–2795, Nov., 2012.
  9. B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.
  10. J. Xu, X. Wu, M. Zhao, R. Fan, H. Wang, X. Ma, and B. Liu, “Ultra Low-FOM High-Precision ΔΣ Modulators with Fully-Clocked SO and Zero Static Power Quantizers,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.
  11. B. Verbruggen, M. Iriguchi, and J. Craninckx, “A 1.7mW 11b 250MS/s 2× Interleaved Fully Dynamic Pipelined SAR ADC in 40nm Digital CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 466–467, Feb., 2012.
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13 responses to “ADC Survey: Christmas 2012 update on FOM

  1. Pingback: ADC Survey: Spring 2012 update on FOM state-of-the-art | Converter Passion

  2. It was an interesting reading!
    Wish you a Merry Christmas and a Happy New Year, Mr. Converter Passion!

    • Thanks Dai!
      Thank you also for all the valuable help and discussions during 2012. I wish you a Happy New 2013, rich with energy in your work – except within the actual IC’s themselves, which we hope reach an unprecedented all-time low in energy (per sample) … 😉
      /Bengt

  3. Happy new year! What about the highest speed ADCs’ current progress?

    • What speed “threshold” are you thinking of? Do you mean GS/s or multi-GS/s ADCs?

      • I mean above 1GS/s ADCs, the resolution is also interest since with high fT devices (SiGe or deep-sub micron CMOS) it is not very hard to obtain a 40Gs/s 4 bits ADC, so I think it would be interesting to know the above 1Gs/s sample rate and >6bits resolution ADCs.

        • OK, I’ll have a look. It may take a little while.

          I managed a quick look before. Without discriminating for resolution it hints at a saturation for Walden FOM @ fs >= 1GS/s, but still progress @ fs >= 10GS/s. But I’ll make a more educated statement after looking closer into it.

          /Bengt

          • Thank you for your care. I think it will be useful for everyone to know what is achieved at very high speeds separate from the lowest energy ADCs since it is a different challenge which is very related to used technology.

            Ozgur

          • I saw commercially Fujitsu has a 56Gs/s 8 bits ADC. I do not know if they publish this ADC somewhere. http://www.fujitsu.com/emea/services/microelectronics/dataconverters/chais/index.html

            Also many oscilloscope manufacturers design and produce their own high-speed ADCs in the range of 40-80GS/s.

            Ozgur

            • I can’t remember seeing the CHAIS ADC scientifically published anywhere, but if anyone knows, please let me know so I can include it in future revisions of the survey. It would make quite an interesting paper if Fujitsu chose to submit one. Almost guaranteed to be accepted.

              As impressive as the design may be, though, it’s SNDR vs. input frequency (SNDR: 40dBFS @Fin=1GHz, 36dBFS @Fin=17GHz) is very much in line with the SNRc vs. fin state-of-the-art envelope in Fig. 6.1 of the recently released survey PDF.

              Without downplaying the achievement it is to push sampling rates in this direction, we can still see that this impressive beast seem to suffer from the same physical limits as any other high-speed ADC, and approximately to the same degree.

              Regarding oscilloscopes in that speed range, I guess they are still using data acquisition boards rather than a single ADC IC. But it’s probably going to move towards more integration, e.g., by using circuits like the Fujitsu CHAIS.

  4. Happy new year and best wishes to all the ADC designers! Your website is very interesting and a lot of fun, glad to find it!

  5. Pingback: ADC Survey: Spring 2013 update on FOM | Converter Passion

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