New minor revision: A/D-converter performance evolution (v1.1)

T13001-ThumbNote that the recently released A/D-converter performance evolution “eBook”/PDF, has been incremented to v1.1 due to a mistake with Figure 6.3. The latest release can always be reached from the Document Download page. If you pass links around, be sure to link to that page instead of any direct link to a specific release.

My sincere apologies to the 38 readers who downloaded the document during the first hours.

11 responses to “New minor revision: A/D-converter performance evolution (v1.1)

  1. Hi Dr. Jonsson
    I’ve been following you blog for quite some time. I’ve also started blogging about analog design with emphasis on ADC design. Please check my blog.

    • Great idea 3Sigma, and welcome to the A/MS blogosphere. I see that you’ve found Mixed-Signal Electronics. If you haven’t seen EveryNano Counts yet, I’d like to recommend a visit there too. Both of these bloggers are good friends of mine. They are brilliant scientists and some of the most skilled mixed-signal designers around.

      Thanks for letting me know about your blog. I have now added you to the blogroll.

      Best wishes,


  2. Sorry. Forget to mention the URL.

  3. If the ADC community has concluded that an impasse has been reached with regards to noise floor, then why is it that beam forming systems (massively parallel converters) have no problem with -160dB SNR at multi-megasample rates? It seems to me that as long as the system can drive the ADC input impedance and the power dissipation of the ADC is acceptable, the limit has not yet been obtained.

    • Hi Scott,

      Thank you for your question. On the first part: I’m not sure if “the ADC community” as a whole has really concluded on anything. What I do know, is that I’ve observed the near-total output of the ADC community, and found that ADC output noise levels have indeed leveled out at around -162dB/Hz for scientific ADCs, and slightly better for commercial stand-alone parts.

      These noise limits are “pragmatic” in the sense that, while it could have been possible to push them further by increasing Pdiss, there is also some common understanding what makes an interesting part/publication contrary to what will be perceived simply as a power-hungry monster. As you say, if a lower noise floor is needed, one could for example always lower impedance levels and/or increase sampling caps, and simply accept the resulting power penalty. In this sense, there might not be a hard limit to reach. What we can observe from the empirical data, however, is that the community seems to have reached the limit where a further increase in power vs. performance appears undesirable/unpublishable/unsellable.

      Another way to lower the noise floor is of course to use many ADCs in parallel to convert the same signal, in which case the combined signal power will increase by 3dB more than the combined white noise for each doubling of hardware. I’m not really an expert in beamforming systems, but to the extent that this benefit translates there, one would obviously have some SNR gain from the parallelism you have to have there anyway.

      All my observations are focused on the reported performance of single ADCs.

      I hope this answered your question.

      BTW: Do you have a reference to a system which really has 160dB SNR over a MHz bandwidth after the ADCs? That’s a pretty extreme performance as it is equivalent to at least -220dB/Hz relative noise floor.

      • An ultrasound system is a good example where beam forming is used to combine multiple ADC paths at a single point to produce an image. 160dB Dynamic range is required for such a system.

        • OK. Thanks Scott,

          But SNR and DR can be very different things – particularly at the system level. If the ultrasound system is required to simultaneously detect signals which vary by 160dB, OK. But if the system should have a useful input dynamic range spanning 160dB, it can be achieved with much less SNR in the signal path – e.g., by the use of AGC – as long as one does not have to resolve the entire 160 dB simultaneously. This approach is sometimes seen in ADC papers, where they report very high “DR”, but the actual SNR is much less.

          If you can refer to a specific circuit/device which has ADCs in the signal path, and which measures an SNR of 160dB over 1MHz bandwidth, I’m very interested to know about it. However, if I should stick my neck out a little, I seriously doubt that such a device currently exists.

          • Clearly there is NO IC that has 160dB SNR or DR or … as you, in a polite way stated, this is doubtful. But, if I have a parallel system with 256 x 14-bit ADCs with 30 MSPS pipelined and they are focused simultaneously on a single point inside the body, isn’t that a very high SNR? Granted, and as you point out, this is lots of power. But the equivalent noise resistance is certainly less than a few kohms. Do you agree?

            I’ve not done the FOM calculation, so perhaps the power would place a chart datapoint inside the “impasse” box. Might be an interesting exercise.

            • To be honest, I don’t think there’s any signal path that measures 160dB SNR over multi-MHz BW.

              Which brings me back to where we started: Maybe I misunderstood you, but I interpreted your original question as if you felt that the observation of noise-floor saturation in ADC was somehow in contradiction with your observation that ultrasound systems “have no problem with -160dB SNR at multi-megasample rates“.

              Therefore I challenged the existence of such designs.

              We seem now to have established that there are no such devices or perhaps even signal path. [The one you suggest would yield at most ~100dB SNR from a thermal noise averaging perspective – beamforming effects not considered. In reality it would probably become strictly quantization noise limited already after 4-8x hardware multiplication].

              That leaves us with the “can we improve SNR by burning more power” question. Which answers: Yes, as always!

              If someone is prepared to increase Pdiss by 256x to lower noise, clearly one can achieve lower Rn than those I’ve observed. My observation is only that no one ever reported such ADC – not that it can’t be done.

              However, when it comes to ADCs with a reasonable P vs. performance ratio – stuff that someone would actually buy or publish – we seem to have reached a noise-floor limit.

              • This would be a more enjoyable conversation sitting across the desk from one another (and certainly more efficient). Nevertheless, I think we are talking around each other. Here are my basic points:

                1. I always have a hard time when a claim is made that the technical world, in any domain, has arrived at a fundamental limit. For example:

                Quote: [Earlier this year (2012) at Intel Investor Day, Mark Bohr who overseas much of Intel’s processor research, was quoted as saying, “The end of Moore’s Law is always 10 years away. And, yes, it’s still 10 years away.”]

                Rather, I think the limitations in any industry are founded upon the premise that rewards rarely come to those seeking answers to what others deem as a fundamental limit. Graduate students want to finish their thesis in a reasonable/predictable time so they don’t stick their necks out to far; just strive for incremental improvements in narrow aspects of the problem.

                Industry, likewise, needs to efficiently spend R&D dollars to produce growing sales next year. There is no money for looking 10 years out, taking huge risks that fail more often than they succeed.

                So perhaps the limits in ADC are because of outside phenomenon that are not easily quantified. Moore’s Law is a great example. What makes a prediction become a “Law”. Human involvement.

                Your discussions about the drop off in publications from industry is well founded. And there is a good reason for this. It is a very sophisticated problem to design an interface to an 18-bit SAR converter. As the renowned technical luminary Jim Williams, formerly of LTC, once wrote, very few things in life need more than 18 bits. So industry (including ADI,LLTC,TXN, MXIM, others) are moving their R&D dollars upstream to SOCs with ADCs rather than standalone ADCs.

                The ADC “impasse” curve covers essentially DC to “Light”. So if each of the limited resources studying ADCs focus on a single point along the curve (i.e. reduce power at one data rate with one architecture at one speed, or any combination thereof), the progress in moving the line will be very slow. Which is precisely what the curves show. A new datapoint occurs periodically at different points along the curves slowly moving out the FOM.

                2. I never claimed that there was an IC that could achieve single-handedly 160dB SNR. Rather, my point was that there are systems where multiple ADCs with very high SNRs can be paralleled to exploit the signal to noise averaging phenomenon. So if a system can be envisioned (i.e. what are the limits on parallelization?) that is theoretically boundless, who can say we have arrived at a limit? Looking at what’s available today (vis-a’-vis integrated power efficiency) to claim a limit has been achieved is not an engineer’s job, but rather the job of a corporate executive deciding where to invest dollars for the quickest ROI.

                3. It appears you agree with the claim that if power is ignored, then SNR limits start moving out. But then you qualify that by essentially saying that limit is reached because power efficiencies are limiting. Again, I don’t see how you can make this claim. Just because you or I can’t today point to a data sheet from Analog Devices with 160dB SNR doesn’t mean that the impasse line can’t be surpassed with innovations in power efficiency or new architectures or whatever.

                Summarily, as engineers, I think it wise to keep an open mind and not proclaim things are limited simply because a chart can be drawn. Things are limited primarily because of other influences such as the lack of investment money available, graduate students need to make a living soon, ADC experts typically work for companies where openness is rewarded with legal problems, etc. What performance would the LHC at CERN achieve if the budget were $1000B: a practical amount if the leading nations of the world proclaimed the study of particle physics as a priority?

                John Kennedy in the early 1960’s made it a priority for the United States to place a man on the moon before 1970. And it became a reality because the money and focus was a priority. This is not likely to happen in ADCs. But that doesn’t mean there is a fundamental limiting wall standing in front of progress on ADC technology.

                Thanks for the dialogue. I hope I’ve made my simple claim more clear. As an engineer and scientist, I just have a problem when scientific limits are claimed by other scientists simply because they can draw a line on a chart.


              • I have come up with the definition of a chart where I would begin to seriously consider claims about FOM limits.

                Show me a chart where at the bottom there are random points spread across the x-Axis and as one goes up the y-Axis the point density increases such that at the “impasse” curve the line is solid and wide with lots of near coincident points. Then I will begin to believe there may be a fundamental scientific limit at play.

                The charts I’ve seen to date look like random scatter plots with points all over the place. No doubt representative of the researcher’s particular focus at the time. The charts show the progress in time.

                The FOM chart I looked at from Murman (Stanford) actually shows a high density of points at the center of the scatter, not at the edge of a line!!! Probably a heavy historical focus at the time for some unknown reason.


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