**ADC ENERGY EFFICIENCY**: As a complement to the previous post, the energy vs. resolution is compared for Nyquist ADCs and ∆∑-modulators (DSM) in this post.

# Class differences

Although it’s good to get an overall view of the landscape first, the previous post didn’t reveal any detail other than the basic shape, and the state-of-the-art border or envelope. We can get additional insight if we divide the data set by A/D-converter ** class**. Every converter has been sorted into one of five classes:

- Asynchronous
- ∆∑-modulator
- Nyquist
- Narrow-band
- Other

**Asynchronous** means *truly* asynchronous, and does not include ADCs where the input is synchronously sampled and only the conversion is self-timed or ripple-through. **Narrow-band** is any converter other than ∆∑ for which the dynamic performance was calculated over a bandwidth lower than *f _{s}*/2.

**Other**is obviously the catch-all class for anything that didn’t fit in the other four.

Nearly all the data is in the **DSM** and **Nyquist** classes, so I have only used those two classes to render the *E _{s}* vs. ENOB plot in Fig. 1. The global envelope is entirely defined by DSM and Nyquist converters. The envelope corner points [1]-[6] from the previous post are still annotated with first-author names, and a few more that are interesting for this discussion have been added as well [8]-[14].

As you can see from Fig. 1, the two state-of-the-art envelopes have very similar overall form: The energy seems to be limited by thermal noise constraints at higher resolutions, and they both level out to a constant *E _{s}*, or at least a curve with much less slope at lower resolutions.

The main difference is that the DSM envelope defines the global state-of-the-art at *high* resolutions, and Nyquist converters define it for *low* to *medium* resolution. The transition point is currently at **12-b ENOB**. Power-efficient ∆∑-modulators seem to have a noise-limited energy per sample from the 22-b ENOB reported by *Naiknaware* [6] down to the 12 bits reported by *Shu* [14]. Below 12 bits, the envelope quickly shifts to a much *weaker dependency of resolution* – not unlike the plateau observed in the previous post.

In comparison, the best Nyquist ADCs follow the thermal-noise energy model (or a slightly steeper slope) from the 15-b ENOB reported for SAR ADCs by *Leung* [7] and *Hurrell* [8] to the SAR ADCs reported by *Harpe* [4] and *Liou* [3] with 10 and 9-b ENOB, respectively. Below 9-b, I consider the envelope to be almost constant, as discussed in the previous post.

I guess you all observed the keyword **SAR** in the above paragraph, didn’t you? The SAR architecture defines more or less the entire shape of the Nyquist envelope, even if there are additional architectures along the plateau.

# Energy bounds for low-resolution DSM

I hope there will soon be a theoretical analysis like [15] and [16] for ∆∑ too (*please let me know if there is one already*). Until then, we have to resort to empirical data. As briefly discussed in the previous post, it’s interesting to understand why the envelope breaks away from the thermal noise limit in the way it does, also for DSM. Are we looking at the same matching/min-size limits as suggested in a comment to the previous post. Lack of data? Lack of the “right” attempts? Limited expectations or other psychological barriers?

Since ∆∑-modulators are often viewed as “high-resolution”, I wanted to investigate the possible scarcity of data below the 12-b breakpoint around *Shu* [14]. Figure 2 shows how the highest ENOB reported in each paper distributes in the underlying data set. Eyeballing the histogram suggests that maybe as much as 40% of the DSM publications report a peak ENOB < 12-b, so “lack of attempts” can probably not explain why the envelope appears to degrade so quickly.

It is beyond the scope of this post to go really deep into the possible reasons for the “plateau-ish” low-resolution region for DSM, but I may return to investigate the composition of experimental data further to see if it can shed some light. For this post I mainly intended to show what the empirical data looks like. I also want to highlight two additional features of the DSM plateau:

*E*is 1–2 orders of magnitude higher than for Nyquist converters._{s}- The low-resolution envelope is defined by more unusual circuit implementations: Modulators presented by
*Daniels*[13],*Wismar*[11] and*Kim*[10] are all**VCO-based**, whereas*Chen*[12] used a**passive ∆∑-loop**where only the comparator is active.

**Why the 10–100X difference to Nyquist converters, then?** From what I can see, most of the Nyquist converters that populate the low-energy envelope are the result of going to great lengths to weed out anything that has *static current*, and anything that *switches faster or more often than it has to*. Since the very foundation of oversampling is to evaluate the circuit state much more often than the Nyquist sampling rate, I assume it will be difficult to close the gap between these two envelopes.

But that’s me. Perhaps you have some idea how it could be done, or how to prove it isn’t possible?

As always, you are welcome to share your own thoughts and interpretations of the data.

# Further reading

If you are curious to see what a more detailed breakdown by architecture would look like, you may find the plot in [17] interesting. Beware, though, that the data used in [17] does not include the most recent 400 or so papers from the last three years. Also, the plot is no masterpiece of readability 😉

Perhaps I need to do a new architectural study soon.

#### References

- B. Javid, and P. Heydari, “A 4-bit 12GS/s Data Acquisition System-on-Chip Including a Flash ADC and 4-Channel DeMUX in 130nm CMOS,”
*Proc. of IEEE Custom Integrated Circ. Conf. (CICC)*, San Jose, California, USA, pp. 1–4, Sept., 2012. - G. Van der Plas and B. Verbruggen, “A 150 MS/s 133 µW 7 bit ADC in 90 nm Digital CMOS,”
*IEEE J. Solid-State Circuits*, Vol. 43, pp. 2631-2640, Dec., 2008. - C.-Y. Liou, and C.-C. Hsieh, “A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with Charge-Average Switching DAC in 90nm CMOS,”
*Proc. of IEEE Solid-State Circ. Conf. (ISSCC)*, San Francisco, USA, pp. 280–281, Feb., 2013. - P. Harpe, E. Cantatore, and A. van Roermund, “A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction,”
*Proc. of IEEE Solid-State Circ. Conf. (ISSCC)*, San Francisco, USA, pp. 270–271, Feb., 2013. - J. Xu, X. Wu, M. Zhao, R. Fan, H. Wang, X. Ma, and B. Liu, “Ultra Low-FOM High-Precision ΔΣ Modulators with Fully-Clocked SO and Zero Static Power Quantizers,”
*Proc. of IEEE Custom Integrated Circ. Conf. (CICC)*, San Jose, California, USA, pp. 1–4, Sept., 2011. - R. Naiknaware, and T. Fiez, “142dB ∆∑ ADC with a 100nV LSB in a 3V CMOS Process,”
*Proc. of IEEE Custom Integrated Circ. Conf. (CICC)*, Orlando, USA, pp. 5-8, May, 2000. - K. Y. Leung, K. Leung, and D. R. Holberg, “A Dual Low Power ½ LSB INL 16b/1Msample/s SAR A/D Converter with on-chip Microcontroller,”
*Proc. of IEEE Asian Solid-State Circ. Conf. (ASSCC)*, Hangzhou, China, pp. 51-54, Nov., 2006. - C. P. Hurrell, C. Lyden, D. Laing, D. Hummerston, and M. Vickery, “An 18 b 12.5 MS/s ADC With 93 dB SNR,”
*IEEE J. Solid-State Circuits*, Vol. 45, pp. 2647-2654, Dec., 2010. - T. Chalvatzis, and S. P. Voinigescu, “A 4.5 GHz to 5.8 GHz Tunable ∆∑ Digital Receiver with Q enhancement,”
*IEEE MTT-S International Microwave Symp. Digest*, Atlanta, USA, pp. 193-196, June, 2008. - J. Kim, T.-K. Jang, Y.-G. Yoon, and S. Cho, “Analysis and Design of Voltage-Controlled Oscillator-Based Analog-to-Digital Converter,”
*IEEE Trans. Circuit and Systems, Pt. I*, Vol. 57, pp. 18-30, Jan., 2010. - U. Wismar, D. Wisland, and P. Andreani, “A 0.2V 0.44µW 20 kHz Analog to Digital ∑∆ Modulator with 57 fJ/conversion FoM,”
*Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC)*, Montreux, Switzerland, pp. 187-190, Sept., 2006. - F. Chen, S. Ramaswamy, and B. Bakkaloglu, “A 1.5V 1mA 80dB Passive ΣΔ ADC in 0.13μm Digital CMOS Process,”
*Proc. of IEEE Solid-State Circ. Conf. (ISSCC)*, San Francisco, California, pp. 54-65, Feb., 2003. - J. Daniels, W. Dehaene, M. Steyaert, and A. Wiesbauer, “A 0.02mm
^{2}65nm CMOS 30MHz BW All-Digital Differential VCO-based ADC with 64dB SNDR,”*Symp. VLSI Circ. Digest of Technical Papers*, Honolulu, USA, pp. 155-156, June, 2010. - Y.-S. Shu, J.-Y. Tsai, P. Chen, T.-Y. Lo, and P.-C. Chiu, “A 28fJ/conv-step CT ΔΣ Modulator with 78dB DR and 18MHz BW in 28nm CMOS Using a Highly Digital Multibit Quantizer,”
*Proc. of IEEE Solid-State Circ. Conf. (ISSCC)*, San Francisco, USA, pp. 268–269, Feb., 2013. - T. Sundström, B. Murmann, and C. Svensson, “Power dissipation bounds for high-speed Nyquist analog-to-digital converters,”
*IEEE Trans. Circuits and Systems, pt. I*, vol. 56, no. 3, pp. 509–518, Mar. 2009. - D. Zhang, C. Svensson, and A. Alvandpour, “Power consumption for SAR ADCs,”
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From your final comment, what happens if you take into account the oversampling factor of the DSM? (i.e. assuming all static power is gone, the capacitors switching are minimized and thermal noise is not limit, additional switching power due to OSR should worsen DSM).

For example, what happens if you calculate a FoM where for all types of ADCs you use 2xfB instead of fs? It’s somehow meaningless, but it could further point out to the oversampling being useful only for resolutions >12bits by trading it off with noise.

I hope it makes sense…

In any case congratulations for the blog posts and for sharing your insights

Thanks!

Do you mean to use E = P/(fs*OSR), i.e. normalize to the oversampled sampling rate instead of the equivalent Nyquist fs that I used in the post?

I can look into that.

I probably misunderstood your comment. The energy-per-sample in Fig. 1 is E = P/fs, where fs

isalready the equivalent Nyquist sampling rate, which for DSM is 2*BW.If I calculate the energy-per-oversampled-sample, the DSM dots will divide by their respective OSR, and appear to “improve”.