A/D-converter performance evolution

ABSTRACT: This multiple-post article analyzes the performance evolution over time for monolithic A/D-Converter (ADC) implementations reported in scientific publications. The work is based on an exhaustive search of IEEE journals and conferences central to the field from 1974 to spring 2012, and thus represents a near-exhaustive survey of reported scientific ADC data. Using the full set of historical data, empirically observed evolution trends are analyzed for all key performance parameters, including linearity, thermal noise, sampling jitter, and effective resolution. Evolution of power efficiency in terms of two commonly used figures of merit is also investigated. Performance parameters that appear to be in saturation have been identified. The results can be used to predict the state-of-the-art specifications of future ADCs.

INTRODUCTION: Monolithic A/D-converter integration has evolved exponentially over nearly four decades. In the early days it was a major achievement to implement full converter functionality within a single die, and power dissipation was high although resolution and speed were modest in comparison with today’s expectations [1]-[7]. Thanks to the early work of pioneers and the continuously increasing effort of the research community, ADC performance has shown an exponential improvement with respect to many key parameters that closely resembles Moore’s Law for the maximum number of components on a digital IC [8]-[9]. As more and more of electronic systems move into the digital domain, the evolution of A/D-converter technology is an essential enabling factor for a wide range of applications: Low power and small chip area allows the ADC to be integrated into a larger system-on-chip (SoC), while advancing the sampling rate at a given resolution or the resolution at a given sampling rate improves system performance or enables entirely new kinds of systems to be built. From a system point-of-view, it is therefore crucial to understand the rate of ADC performance evolution, so that system-level roadmaps can be adapted to what is realistically expected from ADC technology at any given time.

Figure 1. Other ADC surveys.

Several authors have presented works that blend evolution surveys and derivations of theoretical physical limits to various degrees. One of the more widely cited publications is the survey by Walden [10], examining the performance evolution estimated from 150 commercial and scientific ADCs reported between 1978 and 1997. Walden’s survey, which had been partially presented in an earlier publication [11], was the first survey based on a larger set of empirical data, and the observed trends for “SNR-bits” was compared to a set of theoretical limits including thermal noise, jitter, comparator metastability, and Heisenberg’s principle of uncertainty. An average evolution rate of 1.5 “SNR-bits” every 8 years was estimated from the data set. Approximately one decade later, Walden published two updated versions of the survey in [12] and [13] based on slightly larger data sets. Le et al. examined the performance of nearly 1000 commercial ADCs released over a period of 20 years [14], and the survey by Murmann [15] is a significant recent contribution to the field, including approximately 260 scientific ADCs reported 1997–2008. Merkel and Wilson surveyed 150 commercial and scientific ADCs with specifications suitable for defense space applications [16]. ADC performance vs. CMOS scaling was investigated by the blogger in a survey based on 1100 scientific papers in [17], and an analysis of ADC performance evolution was also presented in [18]. Other relevant work is found in [19]-[25]. For more on prior art ADC surveys, see A survey of ADC surveys.

Figure 2. ADC paper distribution by source. Only papers reporting measured ADC implementations have been included. Data until Spring 2012.

ABOUT THIS SURVEY: This article reviews the evolution of several key performance parameters based on a set of over 1700 scientific publications published from 1974 to spring 2012. It represents a near exhaustive survey of experimental ADC performance data reported in scientific publications. A steadily increasing number of ADC implementations have been reported in the scientific literature, growing from a handful to well over 100 publications per year. This trend is an indication of the significance given to ADCs, as well as the effort invested in the field. The distribution of publications over time is shown here, and the distribution by source is shown above. Data was collected from an exhaustive survey of ADC papers in the IEEE Journal of Solid-State Circuits and IEEE Transactions on Circuits and Systems, as well as the following conferences: ISSCC, ESSCIRC, CICC, Symposium on VLSI Circuits, ASSCC, GaAs IC Symp, and BCTM. Additional papers from non-exhaustive searches of other sources have also been included. To the best of the author’s knowledge, this makes it the largest and most comprehensive survey of reported scientific ADC implementations to this date. The work presented in this article relates to general performance trends over time, and parameters that impose similar performance limits on a broad range of architectures. As an additional dimension, the data is frequently divided into its delta-sigma modulator (DSM) and Nyquist subsets. A deeper analysis of power-performance trade-offs would require a full breakdown by architecture, since there are significant differences between various architectures [14], [24]. Such a study of architectural differences is well beyond the scope of this article and will be treated elsewhere. The overall conclusion of this survey is that many parameters have improved or evolved exponentially, but several noise-related performance measures appear to have saturated.

For practical reasons, the article has been divided into the following ten posts:

  1. CMOS node adoption
  2. Low-voltage operation – part 1
  3. Low-voltage operation – part 2
  4. Thermal noise
  5. Jitter
  6. Relative noise floor
  7. Linearity (SFDR)
  8. Sampling rate and resolution
  9. Walden FOM
  10. Thermal FOM

Additional remarks

Cite this article as either [26] or [27].

See also …

ADC research trends: Migration to CMOS

ADC survey data


  1. G. L. Baldwin, “A linear delta modulator/demodulator with 10 Mbit/s sampling rate,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), Philadelphia, USA, pp. 192–193, Feb., 1974.
  2. G. L. Baldwin, and S. K. Tewksbury, “Linear delta modulator integrated circuit with 17-Mbit/s sampling rate,” IEEE Trans. Circuit and Systems, Vol. CAS-21, pp. 553–561, June, 1974.
  3. D. R. Breuer, and J. D. Hyde, “10-Bit, 5-Megasample/second monolithic A/D converter,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), Philadelphia, USA, pp. 152–153, Feb., 1976.
  4. A. G. E. Dingwall, and B. D. Rosenthal, “Low-power monolithic COS/MOS dual-slope 11-Bit A/D Converter,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), Philadelphia, USA, pp. 146–147, Feb., 1976.
  5. A. R. Hamadé, and E. Campbell, “A single-chip 8-bit A/D converter,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), Philadelphia, USA, pp. 154–155, Feb., 1976.
  6. F. H. Musa, and R. C. Taft, “A CMOS monolithic 31/2-digit A/D converter,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), Philadelphia, USA, pp. 144–145, Feb., 1976.
  7. R. A. Nordstrom, “High-speed integrated A/D converter,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), Philadelphia, USA, pp. 150–151, Feb., 1976.
  8. G.E. Moore, “Cramming more components onto integrated circuits,” Electronics, Vol. 38, No. 8, Apr. 1965.
  9. G. E. Moore, “No exponential is forever: but “forever” can be delayed!,” IEEE ISSCC, Dig. Tech. Papers, San Francisco, CA, Feb. 2003, pp. 20–23.
  10. R. H. Walden, “Analog-to-digital converter survey and analysis,” IEEE J. Selected Areas in Communications, no. 4, pp. 539–550, Apr. 1999.
  11. R. H. Walden, “Analog-to-digital converter technology comparison,” in Proc. of GaAs IC Symp., pp. 228–231, Oct., 1994.
  12. R. Walden, “Analog-to-digital conversion in the early twenty-first century,” Wiley Encyclopedia of Computer Science and Engineering, pp. 126–138, Wiley, 2008.
  13. R. H. Walden, “Analog-to-digital converters and associated IC technologies,” in Proc. Compound Semiconductor Integrated Circuits Symp., Monterey, Oct. 2008, pp. 1–2.
  14. B. Le, T. W. Rondeau, J. H. Reed, and C. W. Bostian, “Analog-to-digital converters [A review of the past, present, and future],” IEEE Signal Processing Magazine, pp. 69–77, Nov. 2005.
  15. B. Murmann, “A/D converter trends: Power dissipation, scaling and digitally assisted architectures,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 105–112, Sept., 2008.
  16. K. G. Merkel, and A. L. Wilson, “A survey of high performance analog-to-digital converters for defense space applications,” in Proc. IEEE Aerospace Conf., Big Sky, Montana, Mar. 2003, vol. 5, pp. 2415–2427.
  17. B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, Nov. 2010.
  18. B. E. Jonsson, “A survey of A/D-converter performance evolution,” accepted for presentation, IEEE Int. Conf. Electronics Circ. Syst. (ICECS), Athens, Greece, Dec., 2010.
  19. F. Maloberti, F. Francesconi, P. Malcovati, and O. J. A. P. Nys, “Design considerations on low-voltage low-power data converters,” IEEE Trans. Circuits and Systems, pt. I, vol. 42, no. 11, pp. 853–863, Nov. 1995.
  20. Y. Chiu, B. Nicolic, and P. R. Gray, “Scaling of analog-to-digital converters into ultra-deep-submicron CMOS,” in Proc. Custom Integrated Circuits Conf., San Jose, Sept. 2005, pp. 375–382.
  21. S. Kawahito, “Low-power design of pipeline A/D converters,” in Proc. Custom Integrated Circuits Conf., San Jose, Sept. 2006, pp. 505–512.
  22. C. Svensson, S. Andersson, and P. Bogner, “On the power consumption of analog to digital converters,” Proc. of NORCHIP, Linköping, Sweden, pp. 49–52, Nov., 2006.
  23. T. Sundström, B. Murmann, and C. Svensson, “Power dissipation bounds for high-speed Nyquist analog-to-digital converters,” IEEE Trans. Circuits and Systems, pt. I, vol. 56, no. 3, pp. 509–518, Mar. 2009.
  24. B. E. Jonsson, “An empirical approach to finding energy efficient ADC architectures,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011. [PDF @ IMEKO]
  25. B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011. [PDF @ IMEKO]
  26. B. E. Jonsson, “A/D-converter performance evolution,” Converter Passion, Aug., 2012, Available: https://converterpassion.wordpress.com/articles/a-d-converter-performance-evolution
  27. B. E. Jonsson, “A/D-converter performance evolution,” Converter Passion, Aug., 2012, Available: https://converterpassion.wordpress.com

4 responses to “A/D-converter performance evolution

  1. Pingback: A survey of ADC surveys | Converter Passion

  2. Pingback: Now as a free eBook/PDF: A/D-converter performance evolution | Converter Passion

  3. Allan Belcher

    There are other ADC and DAC surveys for state of the art FOM devices published in IEE conference and colloquia proceedings and an ARMMS conference covering the period 1984-

    • Thank you for your comment Allan. The surveys listed above are the ones I’ve come across, but I’m certain there may be others as well. My horizon is a bit IEEE-biased since that’s the literature that I have more easy access to. Also I’ve not included papers where authors compare their own design with a handful of similar devices (or the entire Murmann data set). So, please add references to any surveys you feel I’ve missed here in the comments. Or you can e-mail them to me if you want.


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