Based on the generic ADC FOM [1], and the similarities observed between several FOM permutations found in the literature, generic FOM classes are proposed. The use of generic FOM classes enables simultaneous treatment of groups of FOM with similar properties, without necessarily defining exactly how bandwidth/sample rate/power dissipation, etc. was defined.

# FOM class definitions

Generic FOM classes are defined in the table below. Both the linear and the logarithmic forms are shown. Scaling coefficients are trivial additions, and have been omitted for readability. Similarly, the linear form figures-of-merit have all been written in their “inverted” form in order to simplify comparison with the most commonly used FOM – the “ISSCC FOM”. For more details on the expressions see [1] and [2].

The list of classes is neither complete nor final, but it captures most of the figures-of-merit found in the literature. Effectively, the classification is based on the unique combination of integer values chosen for the coefficients. In practice, which combinations of -2, -1, 0, 1, and 2 were used. A list of all possible classes would be infinite, due to the infinite number of possible permutations, even if only integer values were to be used for the coefficients. But the magnitude of the coefficients has so far always been chosen as zero or one, and in a few exceptions two (**Update**: *J-class FOM use data-fitted arbitrary coefficeints*). For lack of better nomenclature, the classes have been labeled {“A”, “B”, “C”, … }, but suggestions for an improved naming system are welcome.

Linear form | Logarithmic form |
---|---|

# Examples of use

Some examples of how these FOM classes have been used in the literature are given below. Again, this list is not exhaustive, but it gives examples of exactly what parameter and coefficient values were used, and also a reference citation. The reference given might not be the original, and if you are aware of older references I will greatly appreciate if you let me know. If you are – or believe you are – the author that originally proposed a particular FOM, it would be nice to hear from you.

It is understood that, by exploring all the specific parameters listed in [1] (and more), a large number FOM permutations can be derived in addition to those in the tables below. Note also that all linear-form expressions are written in their “*lower-is-better*” form also here, and might therefore be inverted compared to the original citation.

## A-class

Linear form | Logarithmic form | Ref |
---|---|---|

[3] | ||

[4] | ||

[5] | ||

[6] | ||

[7] | ||

[8] |

## B-class

Linear form | Logarithmic form | Ref |
---|---|---|

[9] | ||

[10] | ||

[11] |

NB: DR in needs to be a power ratio and not an amplitude ratio.

## C-class

Linear form | Logarithmic form | Ref |
---|---|---|

[12] | ||

[13] | ||

[14] |

## D-class

Linear form | Logarithmic form | Ref |
---|---|---|

[15] |

## E-class

Linear form | Logarithmic form | Ref |
---|---|---|

[16] |

## F-class

Linear form | Logarithmic form | Ref |
---|---|---|

[17] |

## G-class

Linear form | Logarithmic form | Ref |
---|---|---|

[18] |

## H-class

Linear form | Logarithmic form | Ref |
---|---|---|

[19] |

**Update**: Two more classes added in order to match the list in [20].

## I-class

Linear form | Logarithmic form | Ref |
---|---|---|

[21] |

## J-class

Linear form | Logarithmic form | Ref |
---|---|---|

[22] |

# References

[1] B. E. Jonsson, “A Generic ADC FOM”, *Converter Passion blog*, On-line, https://converterpassion.wordpress.com/a-generic-adc-fom/, Jan., 2011.

[2] B. E. Jonsson, “Linear-to-logarithmic FOM mapping”, *Converter Passion blog*, On-line, https://converterpassion.wordpress.com/linear-to-logarithmic-fom/, Jan., 2011.

[3] G. Emmert, E. Navratil, F. Parzefall, and P. Rydval, “A versatile bipolar monolithic 6-Bit A/D converter for 100 MHz sample frequency,” *IEEE J. Solid-State Circuits*, Vol. SC-15, pp. 1030–1032, Dec., 1980.

[4] *ISSCC-FOM*, Commonly used.

[5] System drivers, *International Technology Review for Semiconductors*, 2009 Update, On-line, http://www.itrs.net

[6] G. Geelen, “A 6b 1.1GSample/s CMOS A/D converter,” *Proc. of IEEE Solid-State Circ. Conf. (ISSCC)*, San Francisco, California, pp. 128–129, Feb., 2001.

[7] D. Draxelmayr, “A 6b 600MHz 10mW ADC Array in Digital 90nm CMOS,” *Proc. of IEEE Solid-State Circ. Conf. (ISSCC)*, San Francisco, California, pp. 264–265, Feb., 2004.

[8] B. E. Jonsson, and R. Sundblad, “ADC’s for sub-micron technologies,” *EE Times Europe*, pp. 29–30, Apr. 21, 2008.

[9] A. M. A. Ali, C. Dillon, R. Sneed, A. S. Morgan, S. Bardsley, J. Kornblum, and L. Wu, “A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter,” *IEEE J. Solid-State Circuits*, Vol. 41, pp. 1846–1855, Aug, 2006.

[10] S. Devarajan, L. Singer, D. Kelly, S. Decker, A. Kamath, and P. Wilkins, “A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS pipeline ADC,” *IEEE J. Solid-State Circuits*, Vol. 44, pp. 3305–3313, Dec., 2009.

[11] S. Rabii, and B. A. Wooley, “A 1.8-V digital-audio sigma-delta modulator in 0.8-µm CMOS,” *IEEE J. Solid-State Circuits*, Vol. 32, pp. 783–795, June, 1997.

[12] T. N. Andersen, A. Briskemyr, F. Telstø, J. Bjørnsen, T. E. Bonerud, B. Hernes, and Ø. Moldsvor, “A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18μm Digital CMOS,” *Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC)*, Leuven, Belgium, pp. 247–250, Sept., 2004.

[13] B. Esperança, J. Goes, R. Tavares, A. Galhardo, N. Paulino, M. Medeiros Silva, “Power-and-area efficient 14-bit 1.5 MSample/s two-stage algorithmic ADC based on a mismatch-insensitive MDAC,” *Proc. of ISCAS*, Seattle, Washington, USA, pp. 220–223, May, 2008.

[14] J. Sauerbrey, T. Tille, D. Schmitt-Landsiedel, and R. Thewes, “A 0.7-V MOSFET-only switched-opamp ∑∆ modulator in standard digital CMOS technology,” *IEEE J. Solid-State Circuits*, Vol. 37, pp. 1662–1669, Dec., 2002.

[15] Y. Chiu, P. R. Gray, and B. Nikolic, “A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR,” *IEEE J. Solid-State Circuits*, Vol. 39, pp. 2139–2151, Dec., 2004.

[16] B. Bechen, T. v. d. Boom, D. Weiler, and B. J. Hosticka, “Theoretical and practical minimum of the power consumption of 3 ADCs in SC technique,” *Proc. of Eur. Conf. Circ. Theory and Design (ECCTD)*, Seville, Spain, pp. 444–447, Aug., 2007.

[17] S. Gambini, and J. Rabaey, “A 1.5MS/s 6-bit ADC with 0.5V supply,” *Proc. of IEEE Asian Solid-State Circ. Conf. (ASSCC)*, Hangzhou, China, pp. 47–50, Nov., 2006.

[18] *Energy per sample*, Commonly used.

[19] W. C. Black, Jr., and D. A. Hodges, “Time interleaved converter arrays,” *IEEE J. Solid-State Circuits*, Vol. SC-15, pp. 1022–1029, Dec., 1980.

[20] B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” *Proc. of 2011 IMEKO IWADC & IEEE ADC Forum*, Orvieto, Italy, pp. 1–6, June 2011. [PDF @ IMEKO]

[21] K. G. Merkel, and A. L. Wilson, “A survey of high performance analog-to-digital converters for defense space applications,” *Proc. IEEE Aerospace Conf.*, Big Sky, Montana, Mar. 2003, vol. 5, pp. 2415–2427.

[22] M. Vogels, and G. Gielen, “Architectural Selection of A/D Converters,” *Proc. of Des. Aut. Conf. (DAC)*, Anaheim, California, USA, pp. 974–977, June, 2003.

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