Tag Archives: ADC

ADC Survey: Spring 2013 update on FOM


Winter seems to be super-glued to Sweden this year, so to illustrate “spring” I had to pick this photo from the archives.

Winter seems to be super-glued to Sweden this year, so to illustrate “spring” I had to pick this photo from the archives: Liverleaf (Hepatica Nobilis) in all its glory.

ADC FOM UPDATE: It’s now “post-ISSCC”, which is a more than sufficient reason to update the survey. If you were lucky enough to attend ISSCC this year, you may be familiar with the progress in A/D-converter figure-of-merit (FOM) since the Christmas 2012 Update. If not, I will summarize it here. This update also covers the most recent issues of IEEE Journal of Solid-State Circuits (JSSC), Transactions on Circuits and Systems pt. I and II, and ADC papers from ISOCC 2012. Unfortunately, the 2012 version of A-SSCC doesn’t seem to have made it into IEEE Xplore yet, so the 11 or so ADC papers that were published there will have to wait until next update. Even without the A-SCCC 2012, the survey now includes 4057 experimental data points extracted from 1810 scientific papers published between 1974 and Q1-2013.

ISSCC/Walden FOM

Already from the paper titles in the ISSCC 2013 Advance Program, it was clear that the previous 2.8 fJ world record by Harpe et al. [1] wasn’t going to stand for long. Of the two papers reporting an improved Walden FOM, the 10-b SAR by Liou and Hsieh [2], National Tsing Hua University, Hsinchu, Taiwan, achieves an impressive 2.4 fJ. Nevertheless, Pieter Harpe and coauthors Cantatore and van Roermund from Eindhoven University of Technology, The Netherlands, keep the leader position through their new 10/12-b SAR [3], achieving 2.2 fJ in 12-b mode.

Clearly, both of the above designs are outstanding works. Something I particularly liked with the Harpe ADC was the elegant way they reduced the impact of comparator noise only for the decision(s) when it is really needed (i.e., when the comparator input is weak). Check it out, and enjoy the beauty of it all.

Another highlight is that Harpe et al. were able to set the new FOM world record and simultaneously push ENOB to 10.1 bits. Since the Walden FOM does not correctly model the energy vs. resolution trade-off for thermal noise limited designs, it is more difficult to achieve a good FOM the higher resolution you have. We’ll take a deeper look into that very soon in future posts. For now we can just conclude that the effort represented by their result is therefore even more admirable.

Additional observations

As observed in the Christmas 2012 Update, state-of-the-art Walden FOM is typically reported at lower-than-nominal supply voltages. This is true also for the present update. If you are aiming to win the FOM race you obviously need to make a really good design in the first place. Then, when you’re measuring, it seems that a good advice would be to sweep the VDD downwards, accept that the circuit becomes slower and noisier, and simply search for the VDD sweet spot where you get the best FOM to report.

Another striking feature is that sub-10fJ Walden FOM has so far been reported from only a handful of countries, of which The Netherlands and Taiwan currently seem to have the initiative. I will probably focus on this geographical aspect in a separate post, so I’ll just leave you with this teaser for now.

Thermal FOM

As in the previous update, no progress is reported beyond the Thermal FOM of 1.1 aJ reported by Xu [4], but for Nyquist ADCs, the Walden FOM winner above [3] is also the new Thermal FOM winner with a new world record of 2.0 aJ. So, double gold medals for Harpe, Cantatore and van Roermund from Eindhoven University of Technology. Excellent job!

I also want to mention that the design by Liou and Hsieh [2] – the silver medalists in the Walden FOM category above – also weigh in as the third best Thermal FOM ever reported for Nyquist ADCs.

There are a few more designs now becoming visible on my “sub-10aJ radar”. Of these, I’d like to point out the ring-amp based ADC by Hershberg et al. [5]. First of all it’s not a SAR. Among low-energy Nyquist ADCs, that’s unusual in itself. Secondly, the authors suggest that Ring Amp realization of ADCs could be a way to beat the noise-floor vs. technology scaling limits predicted for example by myself in [6]. And, as much as I like to be right in my predictions, I still prefer that I am wrong and the ADC field continue to evolve beyond all limits we can see today. So I hope they are right about the Ring Amp ADC, and will follow up with more experimental results to establish that once and for all.

Or … that someone else of you has something even better in your drawer.

Upcoming posts

Unless I get too fascinated with the geographic aspects of low-energy ADC research, the plan is to start looking at the energy vs. performance limits from a mostly empirical perspective. I hope to deliver something that is useful for those of you active in this race.

References

  1. P. Harpe, G. Dolmans, K. Philips, and H. de Groot, “A 0.7V 7-to-10bit 0-to-2MS/s Flexible SAR ADC for Ultra Low-Power Wireless Sensor Nodes,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Bordeaux, France, pp. 373–376, Sept., 2012.
  2. C.-Y. Liou, and C.-C. Hsieh, “A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with Charge-Average Switching DAC in 90nm CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, USA, pp. 280–281, Feb., 2013.
  3. P. Harpe, E. Cantatore, and A. van Roermund, “A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, USA, pp. 270–271, Feb., 2013.
  4. J. Xu, X. Wu, M. Zhao, R. Fan, H. Wang, X. Ma, and B. Liu, “Ultra Low-FOM High-Precision ΔΣ Modulators with Fully-Clocked SO and Zero Static Power Quantizers,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.
  5. B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U.-K. Moon, “Ring Amplifiers for Switched Capacitor Circuits,” IEEE J. Solid-State Circuits, Vol. 47, pp. 2928–2942, Dec., 2012.
  6. B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.

New minor revision: A/D-converter performance evolution (v1.1)


T13001-ThumbNote that the recently released A/D-converter performance evolution “eBook”/PDF, has been incremented to v1.1 due to a mistake with Figure 6.3. The latest release can always be reached from the Document Download page. If you pass links around, be sure to link to that page instead of any direct link to a specific release.

My sincere apologies to the 38 readers who downloaded the document during the first hours.

Now as a free eBook/PDF: A/D-converter performance evolution


Updated (see below)!

I’m happy to see that the “A/D-converter performance evolutionarticle has become the most popular content on Converter Passion. There’s a huge amount of research work put into those ten posts, so I’m glad you liked it.

T13001-ThumbBut even the most die-hard fan of scatter plots and performance trend estimates may find it tiresome to have to click their way through the ten blog posts.  I even feel a bit lost myself from time to time. For your convenience (and mine too), I have therefore made the whole lot available as an “eBook”/PDF, which you can download here (4.8MB). It’s an almost exact replica of the original on-line content, so if you’ve read the original Converter Passion article there’s nothing new here. But it’s likely you find the format much easier to read. I certainly do.

If you’re working with ADCs, you have probably already clicked the link – it’s an absolute no-brainer: A 50-page fully functional PDF with 44 pages of content, 24 illustrations and 92 references. All for free.

Happy reading!

Update 2013-01-07: My sincere apologies to the 40 or so that have downloaded it already, but there was a bug with Fig. 6.3 (it was 6.2 duplicated). The correct graph has now been inserted in v1.1. of the document. Many thanks to EJ & Henk at Catena!

Book Review: Advanced Data Converters


BOOK REVIEW: Are you looking for a more complete data converter overview than you get from Converter Passion blog posts or by maintaining your own library of recent papers? Perhaps you’re just wishing to catch up on the latest technology or get a helicopter view to see what’s outside of your own patch in the data converter field? Have you been longing for a contemporary data converter summary that is easy to read, yet rich with technical detail? Read on to know if Advanced Data Converters by Gabriele Manganaro is the book you’ve been looking for.

Book at a glance

Advanced-Data-ConvertersAdvanced Data Converters is not the regular tech tome. The actual content only spans slightly more than two hundred pages, followed by a comprehensive reference section listing over 400 relevant works. Of the five chapters, two are introductory in nature, and the remaining three respectively covers ADC, DAC and Trends. On first glance this made me wonder if there was actually anything in the book. Don’t worry, though. Advanced Data Converters is a masterpiece of lossless information compression that may even go beyond the limits of information theory as we know it 🙂

Let me say right from the start that this is a really good book. The author is clearly a gifted writer and has delivered a text that simply flows. It reads more like an interesting story than a technical lecture. Although the topic is advanced, the form never gets in the way. It is concise, professional in style, yet sufficiently relaxed and easy on the brain. Most of us can appreciate what an achievement that is.

Key chapters

The chapter on A/D converters includes a review of underused classic architectures now brought back into the game to overcome the challenges imposed by CMOS scaling. Time-interleaving, calibration, and emerging architectures and techniques – often introduced for the same reason – are also discussed. The story told in this chapter is so in tune with what I’ve observed through my own survey that I actually don’t have a single suggestion as to what could have been added or taken out. It is indeed a very accurate and insightful description of how the field has developed lately. The number of different architectures and techniques covered in a relatively limited space is truly impressive.

A slightly different approach was used in the D/A converter chapter, where “precision” DACs where left out in favor of current-steering DACs. Instead, these are given a more thorough treatment – essentially you get a complete rundown on the key design issues for this type of DAC. This worked very well for me. Ending the chapter is an update on the latest developments on high-performance and specialized DACs.

Finally, there’s a chapter on data converter trends. As the faithful Converter Passion reader may suspect, I’m not easily impressed with scatter plots and survey data trends. Quite unsurprisingly, this is the chapter where I’m instantly itching to jump into the discussion, add a few graphs, discuss what the plots actually show, etc. That’s not necessarily a bad thing, though. Just as the previous two chapters inspire the reader to look deeper into emerging ADC/DAC architectures, it is a good thing if this chapter encourages the reader to become a more active and educated user of survey data. Analogous to the rest of the book, the author has managed to collect an impressive amount of information in a very limited space. The ADC part is split between a summary of several surveys by other authors, and some original work using the Murmann data set. The DAC part reflects the present lack of any large DAC survey, and therefore the trends are estimated from a very small set of data.

The more colors, the better ...

The more color, the better …

The book as a whole

Advanced Data Converters does not start from scratch, but from a point where the reader is assumed to be familiar with the basics of data conversion, sampling, signal processing and IC design. There are numerous references to where the basics are treated, and even if the level is “advanced”, it never gets scary or impenetrable. If you’re relatively new to the field, you could very well enjoy the book anyway.

For more senior scientist, designers, or data converter end users, the book is a veritable goldmine of information. It successfully captures just about everything necessary to catch up with the latest data converter developments. It allows you to understand the essential technical issues and driving forces that shape the data converter field. None of the topics are treated in great depth, but the amount and quality of references for further reading is impressive. The book delivers a feature-rich helicopter view of the entire data converter field that encourages further exploration. It also provides you with a solid framework – a “grid of knowledge” – in which you can place your own bits and pieces as you pick them up.

This is not a book that will bypass the 6–8 years it is said to take becoming a reasonably good data converter IC designer. Neither will any other book. But keeping it as a companion will probably ease the pain of those years considerably. It will also make the constantly changing data converter landscape a bit less confusing. This book is both educational and a source of inspiration for new adventures to all of us that feel we have more to learn. If you truly believe you know it all, then it might still be worth buying it solely for the excellent list of references.

FiveYou can probably guess by now, what the rating will be. Since this is the first book review on Converter Passion, I had made a firm decision to save some headroom at the upper end of the full-scale range. That was the plan. But Advanced Data Converters is one of the best written tech books I’ve ever read, so it would not be correct to give it anything but the highest grade – 5 out of 5.

BTW: If your grandmother gave you money for Christmas, this book might be what she had in mind 😉

Find the book at Cambridge University Press

ADC Survey: Christmas 2012 update on FOM


ADC FOM UPDATE: I’ve understood that many Converter Passion readers are the very scientists who advance the state-of-the-art for A/D-converters. You are most certainly keeping a close eye on the progress yourselves. But in case you haven’t had time to scan the output of every major conference and top journal lately, this post will summarize the figure-of-merit (FOM) evolution since the Spring 2012 Update.

What’s new?

This update adds coverage for the 2012 versions of Symposium on VLSI Circuits, ESSCIRC and CICC. Also the most recent issues of IEEE Journal of Solid-State Circuits (JSSC), and Transactions on Circuits and Systems pt. I and II. A total of 64 new sources were added to the survey, so that it now includes 3917 experimental data points extracted from 1772 scientific papers published between 1974 and Oct/Dec 2012.

ISSCC/Walden FOM

As mentioned in the previous update, the 4.4 fJ reported by van Elzakker et al. at ISSCC 2008 [1] has been an impressively persistent world record for “The FOM”

F_{A1} = \dfrac{P}{{2}^{ENOB}\times f_{s}}

It lasted for over four years until June 2012 until Tai et al [2] presented a 3.2 fJ SAR ADC at the IEEE Symposium for VLSI Circuits. Congratulations to the team from National Taiwan University, Taipei, Taiwan for their outstanding achievement. With their 0.35 V design, the NTU team were the new FOM champions between June and August 2012.

In September there was ESSCIRC. This year’s ESSCIRC had no less than four ADCs with a sub-10 fJ FOM [3]-[6]. No extra points for guessing the architecture – yes, they are all SAR. Among the four, the 2.8 fJ, 0.7 V, 7–10-b, flexible SAR by Harpe, et al. [3], is the new winner. The Eindhoven-based team behind the impressive world-record FOM are from the Holst Centre and Eindhoven University of Technology, The Netherlands. Excellent job, indeed! Many greetings from Converter Passion.

Beside the winners, all designs that achieved an FA1 < 10 fJ since the last update are listed below. Their combinations of {FA1, fs, ENOB, technology, VDDmax} are shown. In addition to all being variations of the SAR architecture, they are also close to the 9-b sweet spot for FA1, as predicted in “The path to a good A/D-converter FOM” and [7]. Except for the 7.07-b design by Yoshioka, et al. [6], they are all gathered within a 0.5-b slim interval centered just above 9-b. As explained in [7], this is not by accident.

Another clear trend is to operate the ADC at a lower-than-nominal supply voltage. As you can se from the table, the CMOS nodes range from 180 to 45 nm, but all six are run at low or ultra-low voltage. This is directly beneficial as it reduces the digital switching power. It is also likely to cause the converter to become limited by analog noise, which is pretty much a requirement when you’re aiming for energy-optimal operation.

FOM [fJ] Speed [S/s] ENOB Node [nm] VDD [V] 1st Author Ref
2.8 2M 9.31 90 0.7 Harpe [3]
3.2 100k 9.06 90 0.35 Tai [2]
3.9 2M 9.29 65 0.7 Yin [4]
4.5 1k 8.80 65 0.6 Zhang [5]
6.1 1.3M 7.07 45 0.4 Yoshioka [6]
8.0 200k 9.33 180 0.6 Huang [8]

What’s in the future?

It seems that a larger body of research efforts are now catching up with the rather extreme step taken by van Elzakker et al. The region below 10 fJ is rapidly becoming more densely populated. Within a six months period we saw two new world records, and with so much focus on this particular performance measure, we are likely to see more. In fact, judging from the titles in the ISSCC 2013 advance program, there are already two designs below 2.8 fJ lining up to be presented there. Perhaps more. Wish I could go there too.

Historically, the state-of-the-art FOM has mainly been reported in JSSC and at ISSCC, with the occasional publication at other conferences. As noted above, we can expect more to come out of ISSCC in the future, but ESSCIRC has clearly raised its profile with respect to ADC FOM in this millennium. Looking at the number of unique publications advancing the state-of-the-art FOM over time sorted by source publication, we get the “market share” of world records for each conference/journal, as shown in Fig. 1. Since the data between 2000 and 2012 consists of only 7 unique FOM advancements, we can’t be too sure about the trends. But it certainly makes ESSCIRC look good, doesn’t it?

Pie charts

Fig. 1. Where was the state-of-the-art FOM published? (a) Accumulated total (b) 1982–1999 (b) 2000–2012. [Click to enlarge]

Thermal FOM

As discussed in a previous post, the overall evolution of the “Thermal FOM”

F_{B1} = \dfrac{P}{{2}^{2\times ENOB}\times f_{s}}

over time has slowed down, and as explained in [9] it may not improve much over technology scaling. It is therefore no surprise that the overall FB1 remains unchanged at the 1.1 aJ reported by Xu [10].

Thermal FOM for Nyquist ADCs

New thermal-FOM champions for Nyquist converters are actually the same as the Walden-FOM winners above: First, the design by Tai et al. [2] nudged the previous 6.6 aJ record by Verbruggen et al. [11] down to 6.0 aJ. After a few months, Harpe et al. took the thermal FOM down to 4.4 aJ, which is the current world record.

Final words

All papers highlighted in this update represent considerable efforts and significant achievements with respect to energy efficiency. It was a joy reading them, and it will be exciting to see how far this evolution will take us.

To the blog readers that celebrate Christmas, I wish you a Merry one – to the rest, a Joyful Season. To all of us, a Happy New Year!

Next up is a book review, which I hope to post soon.

<- Previous FOM update

References

  1. M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.
  2. H.-Y. Tai, H.-W. Chen, and H.-S. Chen, “A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS,” Symp. VLSI Circ. Digest of Technical Papers, Honolulu, USA, pp. 92–93, June, 2012.
  3. P. Harpe, G. Dolmans, K. Philips, and H. de Groot, “A 0.7V 7-to-10bit 0-to-2MS/s Flexible SAR ADC for Ultra Low-Power Wireless Sensor Nodes,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Bordeaux, France, pp. 373–376, Sept., 2012.
  4. G. Yin, H.-G. Wei, U-F. Chio, S.-W. Sin, S.-P. U, Z. Wang, and R. P. Martins, “A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Bordeaux, France, pp. 377–380, Sept., 2012.
  5. D. Zhang, and A. Alvandpour, “A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Bordeaux, France, pp. 369–372, Sept., 2012.
  6. K. Yoshioka, A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with Wide Range Threshold Configuring Comparator,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Bordeaux, France, pp. 381–384, Sept., 2012.
  7. B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, June 2011. [PDF @ IMEKO]
  8. G.-Y. Huang, S.-J. Chang, C.-C. Liu, and Y.-Z. Lin, “A 1-μW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications,” IEEE J. Solid-State Circuits, Vol. 47, pp. 2783–2795, Nov., 2012.
  9. B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.
  10. J. Xu, X. Wu, M. Zhao, R. Fan, H. Wang, X. Ma, and B. Liu, “Ultra Low-FOM High-Precision ΔΣ Modulators with Fully-Clocked SO and Zero Static Power Quantizers,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.
  11. B. Verbruggen, M. Iriguchi, and J. Craninckx, “A 1.7mW 11b 250MS/s 2× Interleaved Fully Dynamic Pipelined SAR ADC in 40nm Digital CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 466–467, Feb., 2012.