Tag Archives: area

Going to Linköping … Yes, Yes, Yes!!

Curves like these can be really useful if you're going for small chip area. Those who attend ECCTD 2011 will get the full picture and learn what's on the X and Y axes.

You’d be forgiven to think that, with all the praise I recently gave to Italy and the IWADC conference, there’s no room in my heart for any other conference or location. But going to the European Conference on Circuit Theory and Design in Linköping, Sweden will be very special. The location isn’t nearly as exotic to me as Italy – quite the opposite in fact. I used to study in Linköping, and I was also a PhD student at the very department that is hosting the conference. What is special with Linköping is that it’s the city I used to call home for about 15 years of my life – 15 good years filled with memorable moments, good friends and talented engineers and scientists. It’s a nice Swedish town, and I highly recommend you to go there. ECCTD 2011 offers the perfect excuse.

If, like me, you’re also interested in what’s actually presented at the conference, it too is an excellent reason to go there. I guess there will be a conference program up on the conference site sooner or later. Until then I can only tell you about my contribution “Area Efficiency of ADC Architectures”, which I was very glad to get accepted. No extra points for guessing the general topic of the paper, and I’m not going to spoil the fun by telling you everything about it. Suffice to say that it’s another huge survey of scientific A/D-converter achievements. This time we’ll take a first look at the area-efficiency of various ADC architectures at different speed/resolution specifications. It exemplifies a small fraction of the EDO methodology used by ADMS Design AB, and gives you some overall guidelines to get you started with area-optimized ADC design.

So, if you design ADCs for high volume production and a low manufacturing cost is important … don’t miss this paper.