ADOPTING NEW TECHNOLOGY: The rate at which scientific ADC implementations migrate to newer CMOS technology is discussed in this post. It was previously observed in , using a more one-dimensional approach and data until March 2010. Here, updated ADC survey data is used, and the 2-D distribution of scientific ADC implementation papers over CMOS node and publication year is analyzed. The result is illustrated by the “heat contours” in Fig. 1. Starting with dark blue, the colors represent paper counts of 0, 1, 2, 5, 10, 15, …, and 40/year, respectively.
Observation of technology adoption
Figure 1 illustrates several key aspects of how the scientific ADC community has adopted new process technology:
- The lower edge of the contours represents the early adopters. It defines the state-of-the-art scaling front for ADCs. In  it was estimated that this front scaled by an average factor of two every 5.4 years until 1995. After 1995, the adoption rate increased to 2 X every 3.75 years, which is illustrated by the exponential trend fit. The data points used for the trend estimations are superimposed onto the contour plot.
- The “center-of-mass” illustrates the average node-adoption by the main body of ADC scientists. Although a highly subjective visual estimation, my impression is that the mainstream adoption rate is higher from 180 nm and below. What do you see?
- The horizontal extension of each node reveals its lifetime in scientific publications. Popular nodes can remain active for well over a decade. Therefore, the correlation between CMOS node and publication year is weak. In other words: you can’t make a good observation of the effects of scaling by simply looking at how something evolves over time. Because of the long lifespan of major nodes, they also have time to undergo a maturing process as the collective understanding of how to best use the node accumulates. ADC performance vs. scaling and the concept of maturing nodes was treated in .
- 180 nm appears to be the all-time favorite node for CMOS ADC designs to this date. This was also observed in .
- Nodes as old as 0.35µm are still active in publications.
Adoption rates, systems on chip, and the scaling gap
Traditionally, there has been a lag – or “scaling gap” – between analog/mixed and digital ICs. Digital ASICs have nearly always benefited from using the most recent technology, whereas analog/mixed ICs have faced new design challenges for every step of scaling. Consequentially, ADC designers have lingered in older, or custom, technologies where they knew they could meet the spec, while digital ASIC designers switched to new nodes as soon as possible. This approach was acceptable – perhaps even optimal – as long as ADCs were used as stand-alone components. Moving into the age of the SoC (system on chip), the scaling gap is increasingly unacceptable. The A/D-converters must be on the same chip as the rest of the circuit, and migrating the digital parts backwards is almost never an option. Therefore the gap must close.
Personally, I believe that this SoC-driven need to close the scaling gap is the most likely explanation for the increased rate of early adoption observed in  and mentioned above. If you have any other suggestions, please share them with us in the comments below.
Future ADC scaling
If the current scaling trend should continue, early adopters would implement ADCs in 5.5 nm CMOS by 2020. As mentioned in , that is well below the technologies predicted available for RF/AMS design by 2020 . As the gap closes between analog and digital, we will therefore see a slowdown in adoption rate.
In fact, the RF/AMS data in  suggests that the scaling gap is already quite small. A minimum L = 24 nm for HP logic in 2011 should be compared with the most deeply scaled ADC in 32 nm CMOS, presented by a team from Intel . Since a small lag between digital and RF/AMS ASICs (as well as between technology “year of production” and ADC “year of publication”) may be inevitable, a slowdown in early-adoption ADC scaling could be just around the corner.
 B. E. Jonsson, “A survey of A/D-converter performance evolution,” Proc. of IEEE Int. Conf. Electronics Circ. Syst. (ICECS), Athens, Greece, pp. 768–771, Dec., 2010.
 B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.
 International Technology Roadmap for Semiconductors (ITRS), 2011 Edition [Online]. Available: http://www.itrs.net
 B. R. Carlton, H. Lakdawala, E. Alpman, J. Rizk, Y. W. Li, B. Perez-Esparza, V. Rivera, C. F. Nieva, E. Gordon, P. Hackney, C.-H. Jan, I. A. Young, and K. Soumyanath, “A 32nm, 1.05V, BIST enabled, 10-40MHz, 11-9 bit, 0.13mm2 digitized integrator MASH ΔΣ ADC,” Symp. VLSI Circ. Digest of Technical Papers, Kyoto, Japan, pp. 36–37, June, 2011.