Tag Archives: IC design

ADC research trends: CMOS node adoption


Figure 1. Distribution of CMOS nodes used for scientific ADCs over time. Color represents number of publications. The early adopter state-of-the-art data points are superimposed along with a scaling trend estimated from 1995–2011 data.

ADOPTING NEW TECHNOLOGY: The rate at which scientific ADC implementations migrate to newer CMOS technology is discussed in this post. It was previously observed in [1], using a more one-dimensional approach and data until March 2010. Here, updated ADC survey data is used, and the 2-D distribution of scientific ADC implementation papers over CMOS node and publication year is analyzed. The result is illustrated by the “heat contours” in Fig. 1. Starting with dark blue, the colors represent paper counts of 0, 1, 2, 5, 10, 15, …,  and 40/year, respectively.

Observation of technology adoption

Figure 1 illustrates several key aspects of how the scientific ADC community has adopted new process technology:

  • The lower edge of the contours represents the early adopters. It defines the state-of-the-art scaling front for ADCs. In [1] it was estimated that this front scaled by an average factor of two every 5.4 years until 1995. After 1995, the adoption rate increased to 2 X every 3.75 years, which is illustrated by the exponential trend fit. The data points used for the trend estimations are superimposed onto the contour plot.
  • The “center-of-mass” illustrates the average node-adoption by the main body of ADC scientists. Although a highly subjective visual estimation, my impression is that the mainstream adoption rate is higher from 180 nm and below. What do you see?
  • The horizontal extension of each node reveals its lifetime in scientific publications. Popular nodes can remain active for well over a decade. Therefore, the correlation between CMOS node and publication year is weak. In other words: you can’t make a good observation of the effects of scaling by simply looking at how something evolves over time. Because of the long lifespan of major nodes, they also have time to undergo a maturing process as the collective understanding of how to best use the node accumulates. ADC performance vs. scaling and the concept of maturing nodes was treated in [2].
  • 180 nm appears to be the all-time favorite node for CMOS ADC designs to this date. This was also observed in [2].
  • Nodes as old as 0.35µm are still active in publications.

Adoption rates, systems on chip, and the scaling gap

Traditionally, there has been a lag – or “scaling gap” – between analog/mixed and digital ICs. Digital ASICs have nearly always benefited from using the most recent technology, whereas analog/mixed ICs have faced new design challenges for every step of scaling. Consequentially, ADC designers have lingered in older, or custom, technologies where they knew they could meet the spec, while digital ASIC designers switched to new nodes as soon as possible. This approach was acceptable – perhaps even optimal – as long as ADCs were used as stand-alone components. Moving into the age of the SoC (system on chip), the scaling gap is increasingly unacceptable. The A/D-converters must be on the same chip as the rest of the circuit, and migrating the digital parts backwards is almost never an option. Therefore the gap must close.

Personally, I believe that this SoC-driven need to close the scaling gap is the most likely explanation for the increased rate of early adoption observed in [1] and mentioned above. If you have any other suggestions, please share them with us in the comments below.

Future ADC scaling

If the current scaling trend should continue, early adopters would implement ADCs in 5.5 nm CMOS by 2020. As mentioned in [1], that is well below the technologies predicted available for RF/AMS design by 2020 [3]. As the gap closes between analog and digital, we will therefore see a slowdown in adoption rate.

In fact, the RF/AMS data in [3] suggests that the scaling gap is already quite small. A minimum L = 24 nm for HP logic in 2011 should be compared with the most deeply scaled ADC in 32 nm CMOS, presented by a team from Intel [4]. Since a small lag between digital and RF/AMS ASICs (as well as between technology “year of production” and ADC “year of publication”) may be inevitable, a slowdown in early-adoption ADC scaling could be just around the corner.

References

[1] B. E. Jonsson, “A survey of A/D-converter performance evolution,” Proc. of IEEE Int. Conf. Electronics Circ. Syst. (ICECS), Athens, Greece, pp. 768–771, Dec., 2010.

[2] B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.

[3] International Technology Roadmap for Semiconductors (ITRS), 2011 Edition [Online]. Available: http://www.itrs.net

[4] B. R. Carlton, H. Lakdawala, E. Alpman, J. Rizk, Y. W. Li, B. Perez-Esparza, V. Rivera, C. F. Nieva, E. Gordon, P. Hackney, C.-H. Jan, I. A. Young, and K. Soumyanath, “A 32nm, 1.05V, BIST enabled, 10-40MHz, 11-9 bit, 0.13mm2 digitized integrator MASH ΔΣ ADC,” Symp. VLSI Circ. Digest of Technical Papers, Kyoto, Japan, pp. 36–37, June, 2011.

Back from ECCTD 2011


After the crystal-clear scientific presentations at ECCTD, I'm now back in the mist again.

So, I’m back from ECCTD 2011 since late Wednesday, and up here at the southern edge of the northern half of Sweden, the mornings are misty and the leaves are turning yellow. Visiting Linköping was every bit as pleasant as I had expected. The conference was held at Linköping Konsert & Kongress, which is beautifully located at the center of the city, right next to the Linköping Cathedral.

The conference

The conference was excellently organized by the Electronics Systems division at Linköping University and the conference committee. I was particularly impressed with the student helpers. Not only were they helpful, kind and attentive, but quite a few of them also turned out to be passionate about data-converter research and development [one of the healthier states of the human mind, BTW 😉 ] and we had several interesting conversations on the topic. I couldn’t possibly have felt more welcome.

Professor Borivoje Nikolić speaks about managing variability.

After we all had been welcomed by the conference general chair, prof. Lars Wanhammar, Linköping University, the conference started with a plenary presentation “Managing Variability for Ultimate Energy Efficiency” given by prof. Borivoje Nikolić from UC Berkeley, USA. The conference then split up into various sessions which are described in detail in the program. ECCTD is a rather broad conference, but there were at least three dedicated data-converter sessions: “Sigma-Delta Modulators“, “Data Converters“, and “Pipelined ADCs“. I had the honor of chairing “Pipelined ADCs“, and I presented my own contribution “Area Efficiency of ADC Architectures” in the “Data Converters” session. I might come back to the content of that paper in another post, but in short (for those of you that were not there), it surveys the chip area vs. performance in speed and resolution for just about every ADC implementation reported in the scientific literature all the way since 1974 – approximately 1500 papers. A normalized area measure

A_{Q} = \dfrac{A}{{2}^{ENOB}}

was proposed based on the observed correlation between absolute chip area (A) and effective resolution (ENOB). State-of-the-art AQ – a.k.a. “Area per effective quantization step” – was seen to be independent not only of ENOB, but also of sampling rate over a broad range of sampling rates and resolutions, respectively. It is also approximately independent of CMOS process node. Chip area per effective quantization step was then compared for individual architectures, and design guidelines derived for area-optimal ADC architecture selection at any given speed and resolution specification. It was seen that there are large differences in the peak area efficiency achieved with different ADC architectures. There is for example a factor of 3 difference between SAR and pipeline, and a factor of 10 between pipeline and flash. Such big area differences can translate to a lot of money if you’re developing high-volume ADCs. So make sure you get hold of this paper as soon as it comes up on IEEE Xplore.

The blogger as session chair. Photo: Mark Vesterbacka

Professor Mark Vesterbacka, Linköping University had to push the electronics in his mobile phone to the maximum in order to document my chairing efforts in spite of the low light. Thanks for sending the picture.

CWCP winner

I could notice a slight peak in blog visitors yesterday. I assume that many of you wanted to know who won the Connect-with-Converter Passion (CWCP) prize, and I apologize for not being as fast as Dr. J Jacob Wikner who was blogging live from ECCTD and managed to fire away several conference-related post on Mixed-Signal Electronics while ECCTD was still developing. One of them correctly revealing that we had a CWCP winner already after the first day. And the winner is:

CWCP-winner Kiran Kariyannawar

Kiran Kariyannawar from Ericsson AB, who showed the enthusiasm and dedication necessary to win the CWCP prize for ECCTD. Congratulations Kiran! Kiran was there together with other Ericsson colleagues to demonstrate The Connected Tree and how to transmit audio and video signals through the human body. Quite far out compared to most demonstrations I’ve seen at scientific conferences. Very fun (at lest from a tech nerd’s perspective), and I’m sure they will figure out a lot of applications for it eventually, although for now they didn’t seem quite sure what to do with it. At least not with the connected tree. I played a bit with the human-body transmission (by becoming the channel), and I think it could be great for DJ-ing. I was just about to get it to rock big time when I started to realize the other delegates need for less noise and gave it up. If only I had a few more minutes to work out that groove …

The next big thing in DJ-ing? Just intermittently add a human body connected between those metal plates – preferably in a rhythmic pattern – and you're all set.

Other impressions

The conference dinner was held at the Air Force Museum – a place I’m likely to return to again to have more time to look at everything. Most likely with the rest of the family. A few photos below will give you some idea of the location. Finding unorthodox locations that can make the conference dinner extra memorable is probably a real challenge to most organizers. Unless they start taking us to outer space and back, I believe that the abundant food stations in combination with the breathtaking beauty of sea life shown at Monterey Bay Aquarium (ISCAS 1998) will remain my personal favorite for the rest of my life, but with ECCTD 2011 now being among the top two. Excellent work!

A classic Swedish beauty.

Chopper techniques. Large implementation.

A peaceful dinner ...

A missile of some kind, with a sign in Swedish saying "DO NOT PUSH HERE". Now, how irresistible is that on a scale to ten? Photo: M. Reza Sadeghifar

Having been to a few conferences, you start to recognize some faces that keep coming back. I had the pleasure of meeting delegates I’ve recently met. Some at NORCHIP, some at ICECS, and others at IWADC. It was great seeing you all. That is the real value of going to conferences.

Peace! 

ECCTD 2011 face-recognition. Note that we observed a severe Linköping bias here that might be compensated for in "future work".

Connect with Converter Passion at ECCTD 2011


Hi all, and sorry about the low posting frequency during the summer. Now I’m here again, and this time to announce the Connect with Converter Passion (CWCP) competition for ECCTD 2011 next week. As always, I want to take the opportunity to connect with blog readers, and to give you some visibility.

Same face – new conference

To win the prize (which is the glory of winning + some visibility on this blog), all you need to do is to be the first one to locate me during the conference and claim the prize. Couldn’t be much simpler. Since the Linköping University group that is organizing the conference has a strong history of winning the CWCP prize, I will discriminate slightly against them this time (sorry guys) – but just slightly – to give the rest of you a fair chance. Affiliates of Linköping University will not be allowed to claim the prize until the second day of the conference (Tuesday). But don’t forget to try, because it may still be up for grabs by then.

If you haven’t located me before that, Tuesday is also a safe day to find me, as I’m presenting my ECCTD contribution “Area Efficiency of ADC Architectures” in session T21, Data Converters (starting 15:50). Last chance is around the W33 session, Pipelined ADCs, which I’ll be chairing on Wednesday afternoon.

Looking forward to seeing you in Linköping next week.

The path to a good A/D-converter FOM


Figure 1. ENOB, power, and sampling rate trajectories showing the evolution path to the current state-of-the art FOM.

If you are participating in the scientific competition to report an ever better ADC figure-of-merit (FOM), you will find some pretty useful information in this post. Basically it will tell you where to start “drilling for oil”, and with a bit of persistence (preferably combined with some skill in the art) it might take you all the way to ISSCC 2013. The deadline for ISSCC 2012 is probably a bit too close for anyone to make a full ADC implementation according to these guidelines and still get it back in time from the foundry. But you can always try. I will give you a set of information about design and performance parameters that will enable you to predict quite accurately where in the design space the next state-of-the-art ADC (with respect to FOM) will be located. Remember that it could be your ADC, if you choose to optimize the speed-resolution-power tradeoff for this particular target.

First, let us clarify that we are talking about the most commonly used ADC figure-of-merit of all:

F_{A1} = \dfrac{P}{{2}^{ENOB}\times f_{s}}

Figure 1 illustrates the trajectories of each of the three parameters in FA1 as FA1 improved over time. Click on the image to enlarge it. Only the data points representing an advance of FA1 state-of-the-art, i.e., the monotonic decrease of FA1 over time are used in the plot. Time was also quantized so that only the single best ADC per year appears in the trajectories. The underlying data set is gathered from 1600 scientific papers, and the same as used in [1]-[5]. The FOM axis and the FOM values for each dot are the same for all three plots, while the x axes show the simultaneous values of ENOB, power dissipation and sampling rate, respectively. These are the three parameters used to calculate the FOM, so any systematic trends in their trajectories are likely to be a good direction for a FOM-optimized design.

Figure 2. Approximate trajectory trends suggested by the plots.

Although there is plenty of noise in some of the trajectories, visual inspection suggests the approximate trends indicated in Fig. 2. At least it is my best guesstimate. It is purely ad hoc, and you are of course invited to discuss and refine my estimates by posting comments below. The most obvious trend applies to power dissipation (P), which has reduced by almost six orders of magnitude – from Watts to micro-Watts. At the same time the effective resolution (ENOB) has followed a more noisy, but visible path towards lower (medium) resolutions – from ~14 to currently 9-b ENOB. The change equals a three orders of magnitude increase in error power. Finally, the sampling rates at which state-of-the-art figures-of-merit were achieved have migrated slowly, from ~100 kS/s to 1–10 MS/s, even if state-of-the-art FOMs have occasionally been reported at several GS/s in the past. Looking at the fs trajectory from a purely mathematical curve-fitting perspective, it would not support the trend suggested by the green curve. Weighing in some understanding of the speed-power tradeoff in actual design (described below), it makes a bit more sense. It appears thus, that the FOM is best improved by lowering the power dissipation and accepting a medium resolution, while running at moderate sampling rates.

Understanding the trajectories

In high-resolution ADCs, it can be shown that the power dissipation has a lower limit defined by the size of capacitors sized for a kT/C-noise in line with the target ENOB. The power used to drive these capacitors increase by 4X for every additional bit of resolution – in other words, as {{2}^{2\times ENOB}} . It was shown in [3] and [4] that the break point where power dissipation becomes proportional to {{2}^{2\times ENOB}} is currently @ 9-b ENOB for the most power efficient ADCs. It was also shown in [4] that FA1 will always have a sweet spot at this break point.

Since FA1 (erroneously) presupposes that P is proportional to {{2}^{ENOB}} (rather than {{2}^{2\times ENOB}} ) for P and ENOB to be traded on equal terms, you will always improve FA1 more by lowering P than by increasing ENOB – as long as ENOB ≥ 9. Below the 9-b break point, state-of-the-art P/fs is approximately independent of ENOB [3]-[4],  which makes it meaningless to lower the resolution further, as it would only diminish the {{2}^{ENOB}} factor in FA1 and do very little to reduce P/fs. This is the reason why the trajectories has not migrated to even lower resolutions and dissipations – for example to a pathologically low ENOB with femto-Watt dissipation.

The reason state-of-the-art FA1 values tend to be reported for 0.1–10 MS/s ADCs is perhaps less obvious. A reasonable assumption is that energy per sample (P/fs) increase faster than linearly with fs when sampling rates are pushed further, and therefore moderately fast designs are likely to have a more optimal P/fs at any fixed ENOB.

Cookbook for an optimized FOM

It was shown in [2] that the state-of-the-art FA1 also improves with every step of CMOS scaling. Including the parameter trajectories showed in this post, the recipe for a good A/D-converter FOM would be something like:

  • Use the most deeply scaled CMOS process you possibly can.
  • Aim for 8–9-b effective resolution, and a modest sampling rate.
  • Use the lowest amount of power that will place you at the ENOB sweet spot, and let the measurements decide exactly what fs you should claim in the paper 😉

There are a few more tricks – some of which can be understood from [3] and some that I’ll save for clients and partners – but that’s more or less it. It will obviously help if you’re prepared to go the extra mile with your design, like the current record holders van Elzakker, et al. [6], who introduced multi-step charging of capacitors to further reduce P/fs. Honing your design skills will help too, but essentially you’re now set to go out and design the next big scientific hit … 

Keep trying, and best wishes! 🙂

References

[1] B. E. Jonsson, “A survey of A/D-converter performance evolution,” Proc. of IEEE Int. Conf. Electronics Circ. Syst. (ICECS), Athens, Greece, pp. 768–771, Dec., 2010.

[2] B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.

[3] B. E. Jonsson, “An empirical approach to finding energy efficient ADC architectures,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011. [PDF @ IMEKO]

[4] B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011. [PDF @ IMEKO]

[5] B. E. Jonsson, “Area Efficiency of ADC Architectures,” Accepted for presentation at Eur. Conf. Circ. Theory and Des. (ECCTD), Linköping, Sweden, Aug., 2011.

[6]    M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.

Going to Linköping … Yes, Yes, Yes!!


Curves like these can be really useful if you're going for small chip area. Those who attend ECCTD 2011 will get the full picture and learn what's on the X and Y axes.

You’d be forgiven to think that, with all the praise I recently gave to Italy and the IWADC conference, there’s no room in my heart for any other conference or location. But going to the European Conference on Circuit Theory and Design in Linköping, Sweden will be very special. The location isn’t nearly as exotic to me as Italy – quite the opposite in fact. I used to study in Linköping, and I was also a PhD student at the very department that is hosting the conference. What is special with Linköping is that it’s the city I used to call home for about 15 years of my life – 15 good years filled with memorable moments, good friends and talented engineers and scientists. It’s a nice Swedish town, and I highly recommend you to go there. ECCTD 2011 offers the perfect excuse.

If, like me, you’re also interested in what’s actually presented at the conference, it too is an excellent reason to go there. I guess there will be a conference program up on the conference site sooner or later. Until then I can only tell you about my contribution “Area Efficiency of ADC Architectures”, which I was very glad to get accepted. No extra points for guessing the general topic of the paper, and I’m not going to spoil the fun by telling you everything about it. Suffice to say that it’s another huge survey of scientific A/D-converter achievements. This time we’ll take a first look at the area-efficiency of various ADC architectures at different speed/resolution specifications. It exemplifies a small fraction of the EDO methodology used by ADMS Design AB, and gives you some overall guidelines to get you started with area-optimized ADC design.

So, if you design ADCs for high volume production and a low manufacturing cost is important … don’t miss this paper.