ADC research trends: Migration to CMOS

Figure 1. Scientific “market share” trend for CMOS ADCs.

CMOS TAKE-OVER: I don’t think it will surprise anyone to learn that most experimental ADC implementations are nowadays done in CMOS. Figure 1 shows how the fraction of CMOS ADCs has increased in the scientific output. Last year (2011), over 98% of all papers in the mainstream sources were about A/D-converters implemented in CMOS. While experimental ADC research used to involve bipolar/BiCMOS designs as well, it is now completely dominated by CMOS.

CMOS ADCs were a significant part of the research field already in the early days. There is some transient noise in the beginning, due to the few papers published each year. Knowing the total paper count per year from a previous post, we can see that the curve is stable for all years having a total paper count above 10.

Figure 2 displays the evolution of ADC implementation papers grouped by device type. The taxonomy used here is simplified to {Bipolar, BiCMOS, CMOS, Other}, where the “Other” category includes various FET variations that are not complementary MOS (e.g., JFET or NFET), together with CCD, TFT, optoelectronic and quantum devices. In some papers it was not possible to determine which device type was used (n/a). Figure 3 illustrates the scientific “market share” trends for CMOS/Bipolar/BiCMOS ADCs. The underlying data is the same as in Fig. 2.

I realize that there might be specialized conferences or workshops where you may still find a bipolar ADC, but the graphs are representative of the journals and conferences where the vast majority of IC implementations are reported – including BCTM (IEEE Bipolar/BiCMOS Circuits and Technology Meeting) and CSIC (Annual IEEE Compound Semiconductor Integrated Circuit Symposium).

So, what do you think about the future of bipolar and BiCMOS ADCs? Do they have a place in the future? Is there any application or performance spec where they are the better alternative? Is there any relevant research left to do? My impression is that commercial ADC parts still use at least BiCMOS process options more often than scientific designs do. Why is that? Will they too migrate to 100% CMOS?

In an upcoming related post I hope to look at CMOS scaling and node adoption.

Figure 2. Evolution of paper count per device type.

Figure 3. Evolution of scientific “market share” per device type.

FootnoteS

Data for 2012 was excluded from the graphs since the year is not yet complete. This far, 100% of the surveyed 2012 papers have treated CMOS ADCs.

The term “paper” or “ADC paper” used in this post (and many others) refers to an implementation type of paper, where a measured IC implementation is reported. Simulation-only, and theoretical papers are not included in the survey.

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Australia’s first scientific ADC

Congratulations!

BREAKING NEW GROUND: The ADC landscape is continuously changing – also geographically. To the best of my knowledge, 2012 is the year when Australia became the 30^th nation to successfully implement, measure, and scientifically report, an A/D-converter IC (*). Great news!

Authors Jeffrey Harrison, Michal Nesselroth, Robert Mamuad, Arya Behzad, Andrew Adams, and Steve Avery presented their design in the ISSCC contribution “An LC Bandpass ΔΣ ADC with 70dB SNDR Over 20MHz Bandwidth Using CMOS DACs” [1].

The organization behind this Australian milestone is Broadcom. Arya Behzad is affiliated with Broadcom, San Diego, CA. All other authors are with Broadcom, Sydney, Australia. Excellent job!

Reference

[1] J. Harrison, M. Nesselroth, R. Mamuad, A. Behzad, A. Adams, and S. Avery, “An LC Bandpass ΔΣ ADC with 70dB SNDR Over 20MHz Bandwidth Using CMOS DACs,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 146–147, Feb., 2012.

Footnote

(*) NB: The definition I use is first-author-centric. It looks only at the country of the 1st-author affiliation. It is also focused on the accumulated scientific output of the sources listed here. If you are aware of an earlier Australian ADC implementation, please let me know.

See also …

ADC Survey Data

ADC Survey: Spring 2012 update on FOM state-of-the-art

Will reading tons of ADC papers grow your brain — or wear it out?

Well folks, its the time of year when an A/D-converter survey update is due. Since a significant effort is still invested in the quest for ever-improving figures-of-merit (FOM), I’ll start by firing up the Converter Passion FOM-o-meter  and apply it to the body of ADC science. The latter is here approximated by my pet project – the ADC performance survey.

Including the papers added since last year, the updated survey now has 3628 experimental data points extracted from 1708 scientific papers published between 1974 and April/May 2012. The number of unique ADC implementations will be slightly less, since some papers are full-length versions of conference contributions. The source publications monitored are listed here.

What a difference a year makes …

… or not?

ISSCC/Walden-FOM

Can you believe this: With all the current competition to get a great ISSCC/Walden-FOM

the state-of-the-art (4.4 fJ) reported by van Elzakker et al. at ISSCC four years ago [1] is still number one. Their design really went the extra mile with respect to getting a low energy per sample, and I guess that paid off big time. Well done!

As Michiel commented, it is just a matter of time before someone goes below 4.4 fJ. This is also reflected in the scientific output over the last twelve months. Although the current world record didn’t change, there are several designs that reported an < 10 fJ, and that’s not bad either. They are:

FOM [fJ]	Speed [S/s]	ENOB	Architecture	1st Author	Ref
8.7	2M	8.27	SAR	Sekimoto	[2]
6.8	1k	8.52	SAR	Lu	[3]
6.5	4M	9.4	SAR	Harpe	[4]
6.1	1.1M	7.48	SAR	Shikata	[5]
6.8	10M	10.0	SAR	Verbruggen	[6]
9.7	250M	9.45	SAR	Verbruggen	[6]

The most striking feature is probably that they are all SAR ADCs. Secondly, while they are all impressive efforts, the one that stands out a bit is the design by Verbruggen et al. It maintains a sub-10fJ FOM at a significantly higher sampling rate (250 MS/s) while also reporting the highest resolution [6].

Although it’s beyond the scope of this post, it can be good to keep in mind that there are other aspects to factor in than simply the FOM value when analyzing energy efficiency. It was pointed out by Verbruggen [6] that previous ultra-low FOM ADCs have been reported only at rather low sampling rates or moderate resolution. It is a greater challenge to maintain a low for high sampling rates. Hence, pragmatic limits to the state-of-the-art are speed-dependent. It has also been shown that the limits are both scaling- and resolution-dependent [7, 8], so a perfectly fair comparison between designs is difficult to make. I can pretty much guarantee that I’ll get back to this topic in the future, but for the remainder of this post we’ll just look at the raw FOM numbers as they are.

Thermal FOM

It would have been boring to read another 100+ papers and still have nothing new to report, so I’m very glad to see that the so called “Thermal FOM”

has been improved by over a factor of two through the switched-opamp (SO) based ∆∑ design reported by Xu et al. [9]. Previous state-of-the-art – 2.7aJ reported by Perez et al. [10] – will assume its well-earned place in the Hall of Fame, while we applaud the 1.1 aJ achieved by the Chinese team from Zheijan University and Analog Devices, Shanghai. You’re the best now. Enjoy!

Thermal FOM for Nyquist ADCs

There has also been some evolution among the Nyquist ADCs: The 250MS/s SAR ADC by Verbruggen et al. mentioned above, is actually the new Thermal-FOM champion for Nyquist ADCs as it nudges the previous record [11] from 7.6 to 6.6 aJ. The authors are with imec, Belgium, and Renesas Electronics, Japan. Congratulations!

Old and new winners are always found in the halls of fame for Thermal and Walden FOM, respectively. If you are only interested in checking for the current leaders, the FOM-o-meter gives you both with a single click.

As always: I do believe the information here is correct, but if I’ve misrepresented anyone or forgotten to mention someone that should have been included, just send me an email or post a comment below.

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References

[1] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.

[2] R. Sekimoto, A. Shikata, T. Kuroda, and H. Ishikuro, “A 40nm 50S/s – 8MS/s Ultra Low Voltage SAR ADC with Timing Optimized Asynchronous Clock Generator,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Helsinki, Finland, pp. 471–474, Sept., 2011.

[3] T.-C. Lu, L.-D. Van, C.-S. Lin, C.-M. Huang, “A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/Conversion-Step SAR ADC for Biomedical Applications,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.

[4] P. Harpe, Y. Zhang, G. Dolmans, K. Philips, and H. De Groot, “A 7-to-10b 0-to-4MS/s Flexible SAR ADC with 6.5-to-16fJ/conversion-step,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 472–473, Feb., 2012.

[5] A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS,” IEEE J. Solid-State Circuits, Vol. 47, pp. 1022–1030, Apr., 2012.

[6] B. Verbruggen, M. Iriguchi, and J. Craninckx, “A 1.7mW 11b 250MS/s 2× Interleaved Fully Dynamic Pipelined SAR ADC in 40nm Digital CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 466–467, Feb., 2012.

[7] B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.

[8] B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, June 2011. [PDF @ IMEKO]

[9] J. Xu, X. Wu, M. Zhao, R. Fan, H. Wang, X. Ma, and B. Liu, “Ultra Low-FOM High-Precision ΔΣ Modulators with Fully-Clocked SO and Zero Static Power Quantizers,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.

[10] A. P. Perez, E. Bonizzoni, and F. Maloberti, “A 84dB SNDR 100kHz Bandwidth Low-Power Single Op-Amp Third-Order ΔΣ Modulator Consuming 140μW,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, USA, pp. 478-480, Feb., 2011.

[11] C. P. Hurrell, C. Lyden, D. Laing, D. Hummerston, and M. Vickery, “An 18 b 12.5 MS/s ADC With 93 dB SNR,” IEEE J. Solid-State Circuits, Vol. 45, pp. 2647-2654, Dec., 2010.

The path to a good A/D-converter FOM

Figure 1. ENOB, power, and sampling rate trajectories showing the evolution path to the current state-of-the art FOM.

If you are participating in the scientific competition to report an ever better ADC figure-of-merit (FOM), you will find some pretty useful information in this post. Basically it will tell you where to start “drilling for oil”, and with a bit of persistence (preferably combined with some skill in the art) it might take you all the way to ISSCC 2013. The deadline for ISSCC 2012 is probably a bit too close for anyone to make a full ADC implementation according to these guidelines and still get it back in time from the foundry. But you can always try. I will give you a set of information about design and performance parameters that will enable you to predict quite accurately where in the design space the next state-of-the-art ADC (with respect to FOM) will be located. Remember that it could be your ADC, if you choose to optimize the speed-resolution-power tradeoff for this particular target.

First, let us clarify that we are talking about the most commonly used ADC figure-of-merit of all:

Figure 1 illustrates the trajectories of each of the three parameters in F_A1 as F_A1 improved over time. Click on the image to enlarge it. Only the data points representing an advance of F_A1 state-of-the-art, i.e., the monotonic decrease of F_A1 over time are used in the plot. Time was also quantized so that only the single best ADC per year appears in the trajectories. The underlying data set is gathered from 1600 scientific papers, and the same as used in [1]-[5]. The FOM axis and the FOM values for each dot are the same for all three plots, while the x axes show the simultaneous values of ENOB, power dissipation and sampling rate, respectively. These are the three parameters used to calculate the FOM, so any systematic trends in their trajectories are likely to be a good direction for a FOM-optimized design.

Figure 2. Approximate trajectory trends suggested by the plots.

Although there is plenty of noise in some of the trajectories, visual inspection suggests the approximate trends indicated in Fig. 2. At least it is my best guesstimate. It is purely ad hoc, and you are of course invited to discuss and refine my estimates by posting comments below. The most obvious trend applies to power dissipation (P), which has reduced by almost six orders of magnitude – from Watts to micro-Watts. At the same time the effective resolution (ENOB) has followed a more noisy, but visible path towards lower (medium) resolutions – from ~14 to currently 9-b ENOB. The change equals a three orders of magnitude increase in error power. Finally, the sampling rates at which state-of-the-art figures-of-merit were achieved have migrated slowly, from ~100 kS/s to 1–10 MS/s, even if state-of-the-art FOMs have occasionally been reported at several GS/s in the past. Looking at the f_s trajectory from a purely mathematical curve-fitting perspective, it would not support the trend suggested by the green curve. Weighing in some understanding of the speed-power tradeoff in actual design (described below), it makes a bit more sense. It appears thus, that the FOM is best improved by lowering the power dissipation and accepting a medium resolution, while running at moderate sampling rates.

Understanding the trajectories

In high-resolution ADCs, it can be shown that the power dissipation has a lower limit defined by the size of capacitors sized for a kT/C-noise in line with the target ENOB. The power used to drive these capacitors increase by 4X for every additional bit of resolution – in other words, as . It was shown in [3] and [4] that the break point where power dissipation becomes proportional to is currently @ 9-b ENOB for the most power efficient ADCs. It was also shown in [4] that F_A1 will always have a sweet spot at this break point.

Since F_A1 (erroneously) presupposes that P is proportional to (rather than ) for P and ENOB to be traded on equal terms, you will always improve F_A1 more by lowering P than by increasing ENOB – as long as ENOB ≥ 9. Below the 9-b break point, state-of-the-art P/f_s is approximately independent of ENOB [3]-[4],  which makes it meaningless to lower the resolution further, as it would only diminish the factor in F_A1 and do very little to reduce P/f_s. This is the reason why the trajectories has not migrated to even lower resolutions and dissipations – for example to a pathologically low ENOB with femto-Watt dissipation.

The reason state-of-the-art F_A1 values tend to be reported for 0.1–10 MS/s ADCs is perhaps less obvious. A reasonable assumption is that energy per sample (P/f_s) increase faster than linearly with f_s when sampling rates are pushed further, and therefore moderately fast designs are likely to have a more optimal P/f_s at any fixed ENOB.

Cookbook for an optimized FOM

It was shown in [2] that the state-of-the-art F_A1 also improves with every step of CMOS scaling. Including the parameter trajectories showed in this post, the recipe for a good A/D-converter FOM would be something like:

• Use the most deeply scaled CMOS process you possibly can.
• Aim for 8–9-b effective resolution, and a modest sampling rate.
• Use the lowest amount of power that will place you at the ENOB sweet spot, and let the measurements decide exactly what f_s you should claim in the paper 😉

There are a few more tricks – some of which can be understood from [3] and some that I’ll save for clients and partners – but that’s more or less it. It will obviously help if you’re prepared to go the extra mile with your design, like the current record holders van Elzakker, et al. [6], who introduced multi-step charging of capacitors to further reduce P/f_s. Honing your design skills will help too, but essentially you’re now set to go out and design the next big scientific hit … 

Keep trying, and best wishes! 🙂

References

[1] B. E. Jonsson, “A survey of A/D-converter performance evolution,” Proc. of IEEE Int. Conf. Electronics Circ. Syst. (ICECS), Athens, Greece, pp. 768–771, Dec., 2010.

[2] B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.

[3] B. E. Jonsson, “An empirical approach to finding energy efficient ADC architectures,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011. [PDF @ IMEKO]

[4] B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011. [PDF @ IMEKO]

[5] B. E. Jonsson, “Area Efficiency of ADC Architectures,” Accepted for presentation at Eur. Conf. Circ. Theory and Des. (ECCTD), Linköping, Sweden, Aug., 2011.

[6]    M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.

What parameters should be reported in a good ADC paper?

If you’re anything like me and try to draw as much information as possible out of scientific experiments done by others, you may have been frustrated from time to time over the huge variation in reporting practices between individual scientific authors. Having surveyed over 1600 papers by now, I’ve noted that measurement data reporting philosophies range from having a full set of relevant design and performance parameters (sometimes even including the variation over all circuit samples) down to reporting SNR-only performance for a single input frequency near DC and no mention of things like full-scale range, input amplitude, supply voltage, or anything else that could help the reader to interpret the results. It makes you wonder …

I’ve been contemplating the fact that authors may spend 9-12 months (or 1–1.5% of their lifetime) conceiving, modeling, designing and measuring their ADCs, but when they finally write their papers, some choose to make as little impact as possible by omitting nearly everything that could be of interest to the scientific and engineering community. Imagine yourself spending 1-1.5% of your life earnings on something (that’s like 5 to 7 months salary). Then you’d want it to make a difference, right? So, why not in (some) papers?

I can understand that companies may want to hide some information to avoid helping competitors, and I do understand that academic competition can sometimes be just as fierce. But if neither corporations nor universities feel they can openly report their results, where does that leave our field? Do we really want a “science” where everybody is competing to be the first to come up with something of which they tell nothing?

If not, what can be done about it, and what parameters do you expect to see in a good ADC paper?