# Tag Archives: ISSCC

## The path to a good A/D-converter FOM

Figure 1. ENOB, power, and sampling rate trajectories showing the evolution path to the current state-of-the art FOM.

If you are participating in the scientific competition to report an ever better ADC figure-of-merit (FOM), you will find some pretty useful information in this post. Basically it will tell you where to start “drilling for oil”, and with a bit of persistence (preferably combined with some skill in the art) it might take you all the way to ISSCC 2013. The deadline for ISSCC 2012 is probably a bit too close for anyone to make a full ADC implementation according to these guidelines and still get it back in time from the foundry. But you can always try. I will give you a set of information about design and performance parameters that will enable you to predict quite accurately where in the design space the next state-of-the-art ADC (with respect to FOM) will be located. Remember that it could be your ADC, if you choose to optimize the speed-resolution-power tradeoff for this particular target.

First, let us clarify that we are talking about the most commonly used ADC figure-of-merit of all:

$F_{A1} = \dfrac{P}{{2}^{ENOB}\times f_{s}}$

Figure 1 illustrates the trajectories of each of the three parameters in FA1 as FA1 improved over time. Click on the image to enlarge it. Only the data points representing an advance of FA1 state-of-the-art, i.e., the monotonic decrease of FA1 over time are used in the plot. Time was also quantized so that only the single best ADC per year appears in the trajectories. The underlying data set is gathered from 1600 scientific papers, and the same as used in [1]-[5]. The FOM axis and the FOM values for each dot are the same for all three plots, while the x axes show the simultaneous values of ENOB, power dissipation and sampling rate, respectively. These are the three parameters used to calculate the FOM, so any systematic trends in their trajectories are likely to be a good direction for a FOM-optimized design.

Figure 2. Approximate trajectory trends suggested by the plots.

Although there is plenty of noise in some of the trajectories, visual inspection suggests the approximate trends indicated in Fig. 2. At least it is my best guesstimate. It is purely ad hoc, and you are of course invited to discuss and refine my estimates by posting comments below. The most obvious trend applies to power dissipation (P), which has reduced by almost six orders of magnitude – from Watts to micro-Watts. At the same time the effective resolution (ENOB) has followed a more noisy, but visible path towards lower (medium) resolutions – from ~14 to currently 9-b ENOB. The change equals a three orders of magnitude increase in error power. Finally, the sampling rates at which state-of-the-art figures-of-merit were achieved have migrated slowly, from ~100 kS/s to 1–10 MS/s, even if state-of-the-art FOMs have occasionally been reported at several GS/s in the past. Looking at the fs trajectory from a purely mathematical curve-fitting perspective, it would not support the trend suggested by the green curve. Weighing in some understanding of the speed-power tradeoff in actual design (described below), it makes a bit more sense. It appears thus, that the FOM is best improved by lowering the power dissipation and accepting a medium resolution, while running at moderate sampling rates.

# Understanding the trajectories

In high-resolution ADCs, it can be shown that the power dissipation has a lower limit defined by the size of capacitors sized for a kT/C-noise in line with the target ENOB. The power used to drive these capacitors increase by 4X for every additional bit of resolution – in other words, as ${{2}^{2\times ENOB}}$. It was shown in [3] and [4] that the break point where power dissipation becomes proportional to ${{2}^{2\times ENOB}}$ is currently @ 9-b ENOB for the most power efficient ADCs. It was also shown in [4] that FA1 will always have a sweet spot at this break point.

Since FA1 (erroneously) presupposes that P is proportional to ${{2}^{ENOB}}$ (rather than ${{2}^{2\times ENOB}}$) for P and ENOB to be traded on equal terms, you will always improve FA1 more by lowering P than by increasing ENOB – as long as ENOB ≥ 9. Below the 9-b break point, state-of-the-art P/fs is approximately independent of ENOB [3]-[4],  which makes it meaningless to lower the resolution further, as it would only diminish the ${{2}^{ENOB}}$ factor in FA1 and do very little to reduce P/fs. This is the reason why the trajectories has not migrated to even lower resolutions and dissipations – for example to a pathologically low ENOB with femto-Watt dissipation.

The reason state-of-the-art FA1 values tend to be reported for 0.1–10 MS/s ADCs is perhaps less obvious. A reasonable assumption is that energy per sample (P/fs) increase faster than linearly with fs when sampling rates are pushed further, and therefore moderately fast designs are likely to have a more optimal P/fs at any fixed ENOB.

# Cookbook for an optimized FOM

It was shown in [2] that the state-of-the-art FA1 also improves with every step of CMOS scaling. Including the parameter trajectories showed in this post, the recipe for a good A/D-converter FOM would be something like:

• Use the most deeply scaled CMOS process you possibly can.
• Aim for 8–9-b effective resolution, and a modest sampling rate.
• Use the lowest amount of power that will place you at the ENOB sweet spot, and let the measurements decide exactly what fs you should claim in the paper 😉

There are a few more tricks – some of which can be understood from [3] and some that I’ll save for clients and partners – but that’s more or less it. It will obviously help if you’re prepared to go the extra mile with your design, like the current record holders van Elzakker, et al. [6], who introduced multi-step charging of capacitors to further reduce P/fs. Honing your design skills will help too, but essentially you’re now set to go out and design the next big scientific hit …

Keep trying, and best wishes! 🙂

#### References

[1] B. E. Jonsson, “A survey of A/D-converter performance evolution,” Proc. of IEEE Int. Conf. Electronics Circ. Syst. (ICECS), Athens, Greece, pp. 768–771, Dec., 2010.

[2] B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.

[3] B. E. Jonsson, “An empirical approach to finding energy efficient ADC architectures,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011. [PDF @ IMEKO]

[4] B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011. [PDF @ IMEKO]

[5] B. E. Jonsson, “Area Efficiency of ADC Architectures,” Accepted for presentation at Eur. Conf. Circ. Theory and Des. (ECCTD), Linköping, Sweden, Aug., 2011.

[6]    M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.