Tag Archives: performance

ADC Survey: Spring 2013 update on FOM


Winter seems to be super-glued to Sweden this year, so to illustrate “spring” I had to pick this photo from the archives.

Winter seems to be super-glued to Sweden this year, so to illustrate “spring” I had to pick this photo from the archives: Liverleaf (Hepatica Nobilis) in all its glory.

ADC FOM UPDATE: It’s now “post-ISSCC”, which is a more than sufficient reason to update the survey. If you were lucky enough to attend ISSCC this year, you may be familiar with the progress in A/D-converter figure-of-merit (FOM) since the Christmas 2012 Update. If not, I will summarize it here. This update also covers the most recent issues of IEEE Journal of Solid-State Circuits (JSSC), Transactions on Circuits and Systems pt. I and II, and ADC papers from ISOCC 2012. Unfortunately, the 2012 version of A-SSCC doesn’t seem to have made it into IEEE Xplore yet, so the 11 or so ADC papers that were published there will have to wait until next update. Even without the A-SCCC 2012, the survey now includes 4057 experimental data points extracted from 1810 scientific papers published between 1974 and Q1-2013.

ISSCC/Walden FOM

Already from the paper titles in the ISSCC 2013 Advance Program, it was clear that the previous 2.8 fJ world record by Harpe et al. [1] wasn’t going to stand for long. Of the two papers reporting an improved Walden FOM, the 10-b SAR by Liou and Hsieh [2], National Tsing Hua University, Hsinchu, Taiwan, achieves an impressive 2.4 fJ. Nevertheless, Pieter Harpe and coauthors Cantatore and van Roermund from Eindhoven University of Technology, The Netherlands, keep the leader position through their new 10/12-b SAR [3], achieving 2.2 fJ in 12-b mode.

Clearly, both of the above designs are outstanding works. Something I particularly liked with the Harpe ADC was the elegant way they reduced the impact of comparator noise only for the decision(s) when it is really needed (i.e., when the comparator input is weak). Check it out, and enjoy the beauty of it all.

Another highlight is that Harpe et al. were able to set the new FOM world record and simultaneously push ENOB to 10.1 bits. Since the Walden FOM does not correctly model the energy vs. resolution trade-off for thermal noise limited designs, it is more difficult to achieve a good FOM the higher resolution you have. We’ll take a deeper look into that very soon in future posts. For now we can just conclude that the effort represented by their result is therefore even more admirable.

Additional observations

As observed in the Christmas 2012 Update, state-of-the-art Walden FOM is typically reported at lower-than-nominal supply voltages. This is true also for the present update. If you are aiming to win the FOM race you obviously need to make a really good design in the first place. Then, when you’re measuring, it seems that a good advice would be to sweep the VDD downwards, accept that the circuit becomes slower and noisier, and simply search for the VDD sweet spot where you get the best FOM to report.

Another striking feature is that sub-10fJ Walden FOM has so far been reported from only a handful of countries, of which The Netherlands and Taiwan currently seem to have the initiative. I will probably focus on this geographical aspect in a separate post, so I’ll just leave you with this teaser for now.

Thermal FOM

As in the previous update, no progress is reported beyond the Thermal FOM of 1.1 aJ reported by Xu [4], but for Nyquist ADCs, the Walden FOM winner above [3] is also the new Thermal FOM winner with a new world record of 2.0 aJ. So, double gold medals for Harpe, Cantatore and van Roermund from Eindhoven University of Technology. Excellent job!

I also want to mention that the design by Liou and Hsieh [2] – the silver medalists in the Walden FOM category above – also weigh in as the third best Thermal FOM ever reported for Nyquist ADCs.

There are a few more designs now becoming visible on my “sub-10aJ radar”. Of these, I’d like to point out the ring-amp based ADC by Hershberg et al. [5]. First of all it’s not a SAR. Among low-energy Nyquist ADCs, that’s unusual in itself. Secondly, the authors suggest that Ring Amp realization of ADCs could be a way to beat the noise-floor vs. technology scaling limits predicted for example by myself in [6]. And, as much as I like to be right in my predictions, I still prefer that I am wrong and the ADC field continue to evolve beyond all limits we can see today. So I hope they are right about the Ring Amp ADC, and will follow up with more experimental results to establish that once and for all.

Or … that someone else of you has something even better in your drawer.

Upcoming posts

Unless I get too fascinated with the geographic aspects of low-energy ADC research, the plan is to start looking at the energy vs. performance limits from a mostly empirical perspective. I hope to deliver something that is useful for those of you active in this race.

References

  1. P. Harpe, G. Dolmans, K. Philips, and H. de Groot, “A 0.7V 7-to-10bit 0-to-2MS/s Flexible SAR ADC for Ultra Low-Power Wireless Sensor Nodes,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Bordeaux, France, pp. 373–376, Sept., 2012.
  2. C.-Y. Liou, and C.-C. Hsieh, “A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with Charge-Average Switching DAC in 90nm CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, USA, pp. 280–281, Feb., 2013.
  3. P. Harpe, E. Cantatore, and A. van Roermund, “A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, USA, pp. 270–271, Feb., 2013.
  4. J. Xu, X. Wu, M. Zhao, R. Fan, H. Wang, X. Ma, and B. Liu, “Ultra Low-FOM High-Precision ΔΣ Modulators with Fully-Clocked SO and Zero Static Power Quantizers,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.
  5. B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U.-K. Moon, “Ring Amplifiers for Switched Capacitor Circuits,” IEEE J. Solid-State Circuits, Vol. 47, pp. 2928–2942, Dec., 2012.
  6. B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.
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ADC Survey: Christmas 2012 update on FOM


ADC FOM UPDATE: I’ve understood that many Converter Passion readers are the very scientists who advance the state-of-the-art for A/D-converters. You are most certainly keeping a close eye on the progress yourselves. But in case you haven’t had time to scan the output of every major conference and top journal lately, this post will summarize the figure-of-merit (FOM) evolution since the Spring 2012 Update.

What’s new?

This update adds coverage for the 2012 versions of Symposium on VLSI Circuits, ESSCIRC and CICC. Also the most recent issues of IEEE Journal of Solid-State Circuits (JSSC), and Transactions on Circuits and Systems pt. I and II. A total of 64 new sources were added to the survey, so that it now includes 3917 experimental data points extracted from 1772 scientific papers published between 1974 and Oct/Dec 2012.

ISSCC/Walden FOM

As mentioned in the previous update, the 4.4 fJ reported by van Elzakker et al. at ISSCC 2008 [1] has been an impressively persistent world record for “The FOM”

F_{A1} = \dfrac{P}{{2}^{ENOB}\times f_{s}}

It lasted for over four years until June 2012 until Tai et al [2] presented a 3.2 fJ SAR ADC at the IEEE Symposium for VLSI Circuits. Congratulations to the team from National Taiwan University, Taipei, Taiwan for their outstanding achievement. With their 0.35 V design, the NTU team were the new FOM champions between June and August 2012.

In September there was ESSCIRC. This year’s ESSCIRC had no less than four ADCs with a sub-10 fJ FOM [3]-[6]. No extra points for guessing the architecture – yes, they are all SAR. Among the four, the 2.8 fJ, 0.7 V, 7–10-b, flexible SAR by Harpe, et al. [3], is the new winner. The Eindhoven-based team behind the impressive world-record FOM are from the Holst Centre and Eindhoven University of Technology, The Netherlands. Excellent job, indeed! Many greetings from Converter Passion.

Beside the winners, all designs that achieved an FA1 < 10 fJ since the last update are listed below. Their combinations of {FA1, fs, ENOB, technology, VDDmax} are shown. In addition to all being variations of the SAR architecture, they are also close to the 9-b sweet spot for FA1, as predicted in “The path to a good A/D-converter FOM” and [7]. Except for the 7.07-b design by Yoshioka, et al. [6], they are all gathered within a 0.5-b slim interval centered just above 9-b. As explained in [7], this is not by accident.

Another clear trend is to operate the ADC at a lower-than-nominal supply voltage. As you can se from the table, the CMOS nodes range from 180 to 45 nm, but all six are run at low or ultra-low voltage. This is directly beneficial as it reduces the digital switching power. It is also likely to cause the converter to become limited by analog noise, which is pretty much a requirement when you’re aiming for energy-optimal operation.

FOM [fJ] Speed [S/s] ENOB Node [nm] VDD [V] 1st Author Ref
2.8 2M 9.31 90 0.7 Harpe [3]
3.2 100k 9.06 90 0.35 Tai [2]
3.9 2M 9.29 65 0.7 Yin [4]
4.5 1k 8.80 65 0.6 Zhang [5]
6.1 1.3M 7.07 45 0.4 Yoshioka [6]
8.0 200k 9.33 180 0.6 Huang [8]

What’s in the future?

It seems that a larger body of research efforts are now catching up with the rather extreme step taken by van Elzakker et al. The region below 10 fJ is rapidly becoming more densely populated. Within a six months period we saw two new world records, and with so much focus on this particular performance measure, we are likely to see more. In fact, judging from the titles in the ISSCC 2013 advance program, there are already two designs below 2.8 fJ lining up to be presented there. Perhaps more. Wish I could go there too.

Historically, the state-of-the-art FOM has mainly been reported in JSSC and at ISSCC, with the occasional publication at other conferences. As noted above, we can expect more to come out of ISSCC in the future, but ESSCIRC has clearly raised its profile with respect to ADC FOM in this millennium. Looking at the number of unique publications advancing the state-of-the-art FOM over time sorted by source publication, we get the “market share” of world records for each conference/journal, as shown in Fig. 1. Since the data between 2000 and 2012 consists of only 7 unique FOM advancements, we can’t be too sure about the trends. But it certainly makes ESSCIRC look good, doesn’t it?

Pie charts

Fig. 1. Where was the state-of-the-art FOM published? (a) Accumulated total (b) 1982–1999 (b) 2000–2012. [Click to enlarge]

Thermal FOM

As discussed in a previous post, the overall evolution of the “Thermal FOM”

F_{B1} = \dfrac{P}{{2}^{2\times ENOB}\times f_{s}}

over time has slowed down, and as explained in [9] it may not improve much over technology scaling. It is therefore no surprise that the overall FB1 remains unchanged at the 1.1 aJ reported by Xu [10].

Thermal FOM for Nyquist ADCs

New thermal-FOM champions for Nyquist converters are actually the same as the Walden-FOM winners above: First, the design by Tai et al. [2] nudged the previous 6.6 aJ record by Verbruggen et al. [11] down to 6.0 aJ. After a few months, Harpe et al. took the thermal FOM down to 4.4 aJ, which is the current world record.

Final words

All papers highlighted in this update represent considerable efforts and significant achievements with respect to energy efficiency. It was a joy reading them, and it will be exciting to see how far this evolution will take us.

To the blog readers that celebrate Christmas, I wish you a Merry one – to the rest, a Joyful Season. To all of us, a Happy New Year!

Next up is a book review, which I hope to post soon.

<- Previous FOM update

References

  1. M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.
  2. H.-Y. Tai, H.-W. Chen, and H.-S. Chen, “A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS,” Symp. VLSI Circ. Digest of Technical Papers, Honolulu, USA, pp. 92–93, June, 2012.
  3. P. Harpe, G. Dolmans, K. Philips, and H. de Groot, “A 0.7V 7-to-10bit 0-to-2MS/s Flexible SAR ADC for Ultra Low-Power Wireless Sensor Nodes,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Bordeaux, France, pp. 373–376, Sept., 2012.
  4. G. Yin, H.-G. Wei, U-F. Chio, S.-W. Sin, S.-P. U, Z. Wang, and R. P. Martins, “A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Bordeaux, France, pp. 377–380, Sept., 2012.
  5. D. Zhang, and A. Alvandpour, “A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Bordeaux, France, pp. 369–372, Sept., 2012.
  6. K. Yoshioka, A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with Wide Range Threshold Configuring Comparator,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Bordeaux, France, pp. 381–384, Sept., 2012.
  7. B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, June 2011. [PDF @ IMEKO]
  8. G.-Y. Huang, S.-J. Chang, C.-C. Liu, and Y.-Z. Lin, “A 1-μW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications,” IEEE J. Solid-State Circuits, Vol. 47, pp. 2783–2795, Nov., 2012.
  9. B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.
  10. J. Xu, X. Wu, M. Zhao, R. Fan, H. Wang, X. Ma, and B. Liu, “Ultra Low-FOM High-Precision ΔΣ Modulators with Fully-Clocked SO and Zero Static Power Quantizers,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.
  11. B. Verbruggen, M. Iriguchi, and J. Craninckx, “A 1.7mW 11b 250MS/s 2× Interleaved Fully Dynamic Pipelined SAR ADC in 40nm Digital CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 466–467, Feb., 2012.

ADC performance evolution: Walden figure-of-merit (FOM)


Figure 1. Evolution of best reported Walden FOM for delta-sigma modulators (o) and Nyquist ADCs (#). Monotonic state-of-the-art improvement trajectories have been highlighted. Trend fit to DSM (dotted), and Nyquist (dashed) state-of-the-art. Average trend for all designs (dash-dotted) included for comparison.

POWER EFFICIENCY TRENDS: A series of blog posts on A/D-converter performance trends would not be complete without an analysis of figure-of-merit (FOM) trends, would it? We will therefore take a look at the two most commonly used FOM, starting with the by far most popular:

(1) : F_{A1} = \dfrac{P}{{2}^{ENOB}\times f_{s}}

where P is the power dissipation, fs is Nyquist sampling rate, and ENOB is the effective number of bits defined by the signal-to-noise and-distortion ratio (SNDR) as:

(2) : ENOB = \dfrac{SNDR - 1.76}{6.02}

FA1 is sometimes referred to as the Walden or ISSCC FOM and relates the ADC power dissipation to its performance, represented by sampling rate and conversion error amplitude. The best reported FA1 value each year has been plotted for delta-sigma modulators (DSM) and Nyquist ADCs in Fig. 1. Trajectories for state-of-the-art have been indicated, and trends have been fitted to these state-of-the-art data points. The average improvement trend for all ADCs (2×/2.6 years) is included for comparison.

By dividing the data into DSM and Nyquist subsets, it is seen that delta-sigma modulators have improved their state-of-the-art FOM at an almost constant rate of 2×/2.5 years throughout the existence of the field – just slightly faster than the overall average. State-of-the-art Nyquist ADCs have followed a steeper and more S-shaped evolution path. Their overall trend fits to a 2× improvement every 1.8 years, although it is obvious that evolution rates have changed significantly over time. A more accurate analysis of Nyquist ADC trends should probably make individual fits of the early days glory, the intermediate slowdown, and the recent acceleration phase. This was done in [1] where evolution was analyzed with DSM and Nyquist data merged. However, for simplicity I’ll just stick to the more conservative overall Nyquist trend. [I wouldn’t want anyone to suggest that I’m producing “subjective” or “highly speculative” trend estimates, would I? 😉 ]

Still, if anyone is curious to know … 🙂 … the state-of-the-art data points fit to a 2×/14 months trend between 2000 and 2010. That’s actually faster than Moore’s Law, which is traditionally attributed a 2×/18 months rate [2]-[3]. A new twist on “More than Moore”, perhaps? Even the more conservative overall 2×/21 months trend is close enough to conclude that the state-of-the-art FOM for Nyquist ADCs has developed exponentially in a fashion closely resembling Moore’s Law. And that’s got to be an impressive trend for any analog/mixed circuit performance parameter.

Irrespective of what’s the best fit to data, it should be evident from Fig. 1 that Nyquist ADCs broke away from the overall trend around year 2000, and has since followed a steeper descent in their figures-of-merit. They have also reached further (4.4 fJ) [4] than DSM (35.6 fJ) [5]. The overall trend projects to a 0.2 fJ ADC FOM in 2020. Whether or not that’s possible, we’ll leave for another post. A deeper look at the data also reveals that:

  • The acceleration in state-of-the-art is almost completely defined by successive-approximation (SAR) ADCs [4], [6]-[11], accompanied by a single cyclic ADC [12]. The superior energy efficiency of the SAR architecture was empirically shown in [13].
  • A significant part of the acceleration can be explained by the increased tendency to leave out, for example I/O power dissipation when reporting experimental results – a trend also observed by Bult [14]. The FOM in the graph was intentionally calculated from the on-chip rather than total power dissipation because: (a) ADCs are increasingly used as a system-on-chip (SoC) building block, which makes the stand-alone I/O power for a prototype irrelevant, and (b) Many authors don’t even report the I/O power anymore.
  • FA1 has a bias towards low-power, medium resolution designs rather than high-resolution, and thus benefits from CMOS technology scaling as shown in [15],[16]. An analysis of the underlying data shows that, for the best FA1 every year, the trajectories for ENOB and P follows distinct paths towards consistently lower power and medium resolution. You simply gain more in FA1 by lowering power dissipation than by increasing resolution because (1) does not correctly describe the empirically observed power-resolution tradeoff for ADCs [13],[15].

In order to compare high-resolution ADCs limited by thermal noise, it has therefore been proposed to use a slightly different FOM, sometimes labeled the “Thermal FOM” [17]-[18],

(3) : F_{B1} = \dfrac{P}{{2}^{2\times ENOB}\times f_{s}}

This figure-of-merit will be the topic of the next post.

See also …

ADC survey data

Walden’s survey [19]

References

  1. B. E. Jonsson, “A survey of A/D-converter performance evolution,” Proc. of IEEE Int. Conf. Electronics Circ. Syst. (ICECS), Athens, Greece, pp. 768–771, Dec., 2010.
  2. G.E. Moore, “Cramming more components onto integrated circuits,” Electronics, Vol. 38, No. 8, Apr. 1965.
  3. G. E. Moore, “No exponential is forever: but “forever” can be delayed!,” IEEE ISSCC, Dig. Tech. Papers, San Francisco, CA, Feb. 2003, pp. 20–23.
  4. M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.
  5. J. Xu, X. Wu, M. Zhao, R. Fan, H. Wang, X. Ma, and B. Liu, “Ultra Low-FOM High-Precision ΔΣ Modulators with Fully-Clocked SO and Zero Static Power Quantizers,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.
  6. A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS,” IEEE J. Solid-State Circuits, Vol. 47, pp. 1022–1030, Apr., 2012.
  7. T.-C. Lu, L.-D. Van, C.-S. Lin, C.-M. Huang, “A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/Conversion-Step SAR ADC for Biomedical Applications,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.
  8. S.-K. Lee, S.-J. Park, Y. Suh, H.-J. Park, and J.-Y. Sim, “A 1.3µW 0.6V 8.7-ENOB Successive Approximation ADC in a 0.18µm CMOS,” Symp. VLSI Circ. Digest of Technical Papers, Honolulu, USA, pp. 242–243, June, 2009.
  9. H.-C. Hong, and G.-M. Lee, “A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC,” IEEE J. Solid-State Circuits, Vol. 42, pp. 2161–2168, Oct., 2007.
  10. M. D. Scott, B. E. Boser, and K. S. J. Pister, “An Ultra-Low Power ADC for Distributed Sensor Networks,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Firenze, Italy, pp. 255–258, Sept., 2002.
  11. M. D. Scott, B. E. Boser, and K. S. J. Pister, “An Ultralow-Energy ADC for Smart Dust,” IEEE J. Solid-State Circuits, Vol. 38, pp. 1123–1129, July, 2003.
  12. D. Muthers, and R. Tiekert, “A 0.11mm2 low-power A/D-converter cell for 10b 10MS/s operation,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Leuven, Belgium, pp. 251–254, Sept., 2004.
  13. B. E. Jonsson, “An empirical approach to finding energy efficient ADC architectures,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011. [PDF @ IMEKO]
  14. K. Bult, “Embedded analog-to-digital converters,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Athens, Greece, pp. 52–60, Sept., 2009.
  15. B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011. [PDF @ IMEKO]
  16. B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, Nov. 2010.
  17. A. M. A. Ali, C. Dillon, R. Sneed, A. S. Morgan, S. Bardsley, J. Kornblum, and L. Wu, “A 14-bit 125 MS/s IF/RF sampling pipelined ADC with 100 dB SFDR and 50 fs jitter,” IEEE J. Solid-State Circuits, Vol. 41, pp. 1846–1855, Aug, 2006.
  18. C. Wulff, and T. Ytterdal, “Design of a 7-bit, 200MS/s, 2mW pipelined ADC with switched open-loop amplifiers in a 65nm CMOS technology,” Proc. of NORCHIP, Aalborg, Denmark, Nov., 2007.
  19. R. Walden, “Analog-to-digital conversion in the early twenty-first century,” Wiley Encyclopedia of Computer Science and Engineering, pp. 126–138, Wiley, 2008.

ADC performance evolution: Sampling rate and resolution


ENOB-vs-fs evolution front

Figure 1. Evolution of ENOB vs. fs envelope for scientifically reported ADCs. Current state-of-the art is compared to state-of-the-art envelopes at 1990 (#) and 2000 (<). Theoretical limits for thermal noise @ VFS = 1V (dotted) and jitter (dashed) are indicated.

SPEED/RESOLUTION TRENDS: Previous posts analyzed noise and linearity separately. Another common approach is to review the overall ADC performance in terms of sampling rate and effective resolution ENOB. In Fig. 1, the current state-of-the-art at ~Q1-2012 is compared to the envelopes for 1990 and 2000 in order to show the simultaneous evolution of the two parameters throughout the entire parameter space. SNR-only results have been excluded from this plot because ENOB is not fully defined by SNR. Hence, there is no experimental data available before 1980. By 1990 the curve has assumed the expected shape. Between 1990 and 2000 there is a 1-4 bits improvement across the full range of sampling rates. The main advances were in the 200kS/s – 100MS/s speed range. This corresponds to typical telecommunications specifications – from single-carrier GSM to multi-carrier WCDMA receivers. From year 2000 to present day, the more significant advances were at 12.5 MS/s [1], from 100–250 MS/s, [2]-[3], at 3 GS/s [4], and above 10 GS/s [5]-[7].

The thermal noise limits according to equation (4) in the thermal noise post have been included as a visual guide, using VFS = 1V, = 300 K, and Rn = {50, 2000} Ω. Similarly, the theoretical jitter-limited ENOB at fin fs/2 according to equation (1) in the jitter post has been added for σt = {0.1, 1, 10} ps. The Rn and σt values were deliberately chosen to simplify comparison with a similar plot in Walden’s survey [8] (see also Additional remarks below). Although the jitter limits should preferably be observed from SNR vs. fin (as done in the post on jitter trends), the shape of the state-of-the-art envelopes in Fig. 1 clearly indicate the regions where ADC performance is limited by thermal noise and jitter respectively. The design by Naiknaware et al. [10] is limited by thermal noise, while those by Poulton et al. [5] and Greshishchev et al. [7] are limited by sampling jitter (and/or metastability [9]). At the boundary between thermal noise and jitter limited designs are the ADCs that suffer from both noise sources in equal amount, such as the design by Ali et al. [3]. Designs in this corner put strict demands on the simultaneous design for jitter and thermal noise.

In the next post will take a look at the trends for ADC FOM.

Additional remarks

  • It may seem that the state-of-the-art thermal noise according to Fig. 1 is equivalent to less than 2 kΩ for some designs. This would obviously be in contradiction to the 2.5 and 6.2 kΩ state-of-the-art reported for delta-sigma modulator and Nyquist ADCs, respectively. The thermal noise limits in Fig. 1 are only valid for VFS = 1 Vpp, and the apparently better results here are because of a larger full-scale range, e.g., 2.5 V for [3]. The correct noise-resistance estimations are found here.
  • The corresponding jitter limits in [8] have a 0.5-bit offset because it appears that Walden derives the rms-signal to peak-noise ratio by assuming that the signal is always sampled where the slope is greatest, i.e., in the zero-crossings [9]. In reality, the signal is sampled anywhere along the waveform for all but pathological cases, and therefore the rms slope should be used instead, as was done in this treatment.
  • In [11], the evolution trends for peak sampling rate at fixed minimum ENOB grades {4, 8, 12, 14} bits, and the complementary peak ENOB at fixed minimum sampling rates {10k, 100k, 1M, 100M, 1G} S/s are shown in a style similar to Fig. 3 in the previous post.

See also …

ADC performance evolution: Linearity (SFDR)

ADC performance evolution: Thermal noise

ADC performance evolution: Jitter

ADC performance evolution: Relative noise floor

ADC survey data

References

  1. C. P. Hurrell, C. Lyden, D. Laing, D. Hummerston, and M. Vickery, “An 18 b 12.5 MS/s ADC With 93 dB SNR,” IEEE J. Solid-State Circuits, Vol. 45, pp. 2647–2654, Dec., 2010.
  2. S. Devarajan, L. Singer, D. Kelly, S. Decker, A. Kamath, and P. Wilkins, “A 16b 125MS/s 385mW 78.7dB SNR CMOS pipeline ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 86–87, Feb., 2009.
  3. A. M. A. Ali, A. Morgan, C. Dillon, G. Patterson, S. Puckett, P. Bhorashkar, H. Dinc, M. Hensley, R. Stop, S. Bardsley, D. Lattimore, J. Bray, C. Speir, and R. Sneed, “A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration,” IEEE J. Solid-State Circuits, Vol. 45, pp. 2602-2612, Dec., 2010.
  4. C.-Y. Chen, and  J. Wu, “A 12b 3GS/s Pipeline ADC with 500mW and 0.4 mm2 in 40nm Digital CMOS,” Symp. VLSI Circ. Digest of Technical Papers, Kyoto, Japan, pp. 120–121, June, 2011.
  5. K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernilo, C. Tan, and A. Montijo, “A 20GS/s 8b ADC with a 1MB memory in 0.18μm CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 318–319, Feb., 2003.
  6. S. Shahramian, S. P. Voinigescu, and A. C. Carusone, “A 35-GS/s, 4-bit flash ADC with active data and clock distribution trees,” IEEE J. Solid-State Circuits, Vol. 44, pp. 1709–1720, June, 2009.
  7. Y. M. Greshishchev, J. Aguirre, M. Besson, R. Gibbins, C. Falt, P. Flemke, N. Ben-Hamida, D. Pollex, P. Schvan, and S.-C. Wang, “A 40GS/s 6b ADC in 65nm CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 390–391, Feb., 2010.
  8. R. Walden, “Analog-to-digital conversion in the early twenty-first century,” Wiley Encyclopedia of Computer Science and Engineering, pp. 126–138, Wiley, 2008.
  9. R. H. Walden, “Analog-to-digital converter survey and analysis,” IEEE J. Selected Areas in Communications, no. 4, pp. 539–550, Apr. 1999.
  10. R. Naiknaware, and T. Fiez, “142dB ∆∑ ADC with a 100nV LSB in a 3V CMOS process,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), Orlando, USA, pp. 5–8, May, 2000
  11. B. E. Jonsson, “A survey of A/D-converter performance evolution,” Proc. of IEEE Int. Conf. Electronics Circ. Syst. (ICECS), Athens, Greece, pp. 768–771, Dec., 2010.

ADC performance evolution: Linearity (SFDR)


SFDR-vs-fin evolution

Figure 1. Evolution of SFDR-vs.-fin envelope for scientifically reported ADCs: Current state-of-the art is compared to state-of-the-art envelopes at 1990 (#) and 2000 (<).

LINEARITY TRENDS: After observing trends for technology scaling, voltage scaling, and noise, we have arrived at linearity. As far as the blogger is aware, there has been no large survey on A/D-converter linearity evolution published to this date, except for a recent work by Walden [1], where an “SFDR-bits” vs. fin scatter plot illustrates the state-of-the-art movement between 1999 and 2007 for the outermost corner/edge of the data, based on approximately 175 ADCs. In this post we will instead observe the migration of the entire envelope (state-of-the-art) for SFDR vs. input frequency (and sampling rate) in order to observe how SFDR evolved across multiple frequency ranges between 1990, 2000 and present (~Q1-2012). We will also slice through the data set, and specifically observe SFDR evolution at four very different speed grades of minimum sampling rate. The underlying data is from a survey of 1708 scientific ADC papers published between 1974 and Q1-2012.

ADC linearity trends: SFDR-vs-frequency envelope

While SNR, or an aggregate noise-and-distortion measure such as SNDR, is a sufficient measure of ADC performance for some applications, there are other applications where non-linear distortion is independently specified. Such applications include high-end audio and many wireless communication systems. Wireless communication systems often need to cope with the presence of a strong interferer in the form of a neighboring channel or carrier, while correctly interpreting a weak signal of interest. Without a sufficiently linear signal path, the interfering signal will generate harmonics or intermodulation products that may completely block the in-channel signal. The evolution of ADC linearity is therefore as important as the noise and ENOB evolution.

State-of-the-art envelopes for single-tone spurious-free dynamic range (SFDR) vs. input frequency fin and Nyquist sampling rate fs have been plotted in Fig. 1 and Fig. 2 respectively. Current state-of-the-art at ~Q1-2012 is compared to that of 1990 and 2000 in order to illustrate the evolution over all frequencies. Starting with the envelopes at 1990, the linearity vs. fin and fs is evenly distributed across almost straight lines representing the increasing difficulty to achieve high linearity as the input frequency and sampling rate is increased. The first of the two noticeable performance peaks in Fig. 1 coincide with the 20 kHz audio bandwidth, and the second peak is defined by video and instrumentation ADCs in the frequency range 10-100 MHz. It is evident from both plots that most of the progress from 1990 to the current state-of-the-art was achieved in the first decade 1990-2000 when SFDR vs. fin was improved by 20-40 dB across all input frequencies in the 100 kHz to 1GHz range, and SFDR vs. fs increased by 5-30 dB for the same range of sampling frequencies. Although state-of-the-art linearity has been increased by 5-10 dB over many segments of the frequency range during the last 11 years, Figs. 1 and 2 clearly shows that there has been a slowdown in the evolution of linearity over a broad range of frequencies and speed grades. One noticeable exception is the 30 dB performance lift in the 100-250 MS/s speed range, which reflects the specifications of the more recent wideband radio base-stations (RBS). It was concluded in a previous post that the evolution of communications standard requirements has been a strong driver for ADC jitter performance. Observing that the strongest push of the linearity envelopes also occurred at frequencies and sampling rates matching the specifications for wideband RBS, e.g., [2]-[5], it is concluded that communications applications have been a key driver for ADC linearity as well. This is also the conclusion of Walden in [1]. Another significant achievement during the last decade has been to improve performance at the high-frequency end of the spectrum, with sampling rates above 4 GS/s and input frequencies beyond 1 GHz [6]-[14]. Again, a similar observation is made in [1].

SFDR-vs-fs evolution

Figure 2. Evolution of SFDR-vs.-fs envelope for scientifically reported ADCs: Current state-of-the art is compared to state-of-the-art envelopes at 1990 (#) and 2000 (<).

ADC linearity trends: SFDR by speed grade

Figure 3 shows the evolution of peak SFDR at minimum speed grades of fs ≥ {10k, 1M, 100M, 1G} samples/s. The curves show the monotonically improving upper edge for each subset of survey data. What is included in each subset is defined by the four minimum sampling rate constraints. As in Fig. 1 and Fig. 2, the overall scatter is removed for readability.

My interpretation of Fig. 3 is as follows:

  • 1MS/s ADCs appear to have saturated at an SFDR of 108 dB [15], and have not improved since 1996.
  • 100 MS/s ADCs has slowed-down evolution beyond 100 dB to ~6 dB/decade or less. Current state-of-the-art is 102 dB SFDR [5].
  • At very low, and very high sampling rates there are no signs of saturation yet. For ADCs with fs ≥ 10 kS/s, there has been an almost constant progress of ~9dB/decade from 1992 [16] to 2009 [17].
  • ADCs with fs ≥ 1 GS/s are currently evolving at an accelerated rate of ~3 dB/year. If this rate is maintained, gigasample ADCs could go from 75 dB [18] to upwards of 100 dB SFDR by 2020.
  • The accelerated rate of evolution seen at different times for different speed grades may reflect how research activities migrate to higher and higher sampling rates depending on what applications are in focus. Previously more of a niche product, gigasample ADCs are now becoming a mainstream necessity.
SFDR evolution by speed grades

Figure 3. Scientifically reported ADC implementations: Peak SFDR evolution over time for minimum sampling rates of 10k (o), 1M (#), 100M (<), and 1GS/s (diamond).

Commercial ADC parts

Although not shown here, the results were also compared with the data from 595 commercially released ADC parts. Current state-of-the-art envelope for both sets align well across most of the speed range, with one significant exception: There are already commercial parts with significantly better SFDR than their scientific counterparts at 2 MSPS and below, e.g., AD7766 [19] and AD7986 [20]. Commercial ADCs appear to have evolved beyond their experimental siblings in later years within this speed segment(*).

Another difference is in the paths each subset has followed towards today’s (mostly similar) state-of-the-art. In the GSPS range there is for example MAX 104 [21], specifying 69 dB SFDR at fin = 125 MHz almost a decade before the scientific publication by Taft [22], while scientific efforts seem to have been ahead in other frequency ranges (e.g., below 2MS/s) during earlier years(*).

Linearity trends are therefore more difficult to interpret, and to some degree depend on what products were reported scientifically and not. Such dependency could not be observed for any noise-related parameter analyzed in this series of posts.

(*) Please note that these are only my best guesstimates, as the commercial data set (although large) is not as exhaustive as that for scientific ADCs.

In the next post I plan to review the simultaneous evolution of {ENOB, fs}. Subscribe to the blog, and you won’t miss it.

See also …

ADC performance evolution: Thermal noise

ADC performance evolution: Jitter

ADC performance evolution: Relative noise floor

ADC performance evolution: Low-voltage operation – part 1

ADC performance evolution: Low-voltage operation – part 2

ADC survey data

References

  1. R. Walden, “Analog-to-digital conversion in the early twenty-first century,” Wiley Encyclopedia of Computer Science and Engineering, pp. 126–138, Wiley, 2008.
  2. A. Namdar, and B. H. Leung, “A 400MHz 12b 18mW IF digitizer with mixer inside a ΣΔ modulator loop,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 62–63, Feb., 1999.
  3. A. M. A. Ali, C. Dillon, R. Sneed, A. S. Morgan, S. Bardsley, J. Kornblum, and L. Wu, “A 14-bit 125 MS/s IF/RF sampling pipelined ADC with 100 dB SFDR and 50 fs jitter,” IEEE J. Solid-State Circuits, Vol. 41, pp. 1846–1855, Aug, 2006.
  4. A. M. A. Ali, A. Morgan, C. Dillon, G. Patterson, S. Puckett, P. Bhorashkar, H. Dinc, M. Hensley, R. Stop, S. Bardsley, D. Lattimore, J. Bray, C. Speir, and R. Sneed, “A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration,” IEEE J. Solid-State Circuits, Vol. 45, pp. 2602-2612, Dec., 2010.
  5. R. Payne, M. Corsi, D. Smith, T.-L. Hsieh, and S. Kaylor, “A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC With 100 dBFS SFDR,” IEEE J. Solid-State Circuits, Vol. 45, pp. 2613-2622, Dec., 2010.
  6. K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernilo, C. Tan, and A. Montijo, “A 20GS/s 8b ADC with a 1MB memory in 0.18μm CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 318–319, Feb., 2003.
  7. W. Cheng, W. Ali, M.-J. Choi, K. Liu, T. Tat, D. Devendorf, L. Linder, and R. Stevens, “A 3b 40GS/s ADC-DAC in 0.12μm SiGe,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 262–263, Feb., 2004.
  8. L. Y. Nathawad, R. Urata, B. A. Wooley, and D. A. B. Miller, “A 20GHz bandwidth, 4b photoconductive-sampling time-interleaved CMOS ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 320–321, Feb., 2003.
  9. S. M. Louwsma, A. J. M. van Tuijl, M. Vertregt, and B. Nauta, “A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS,” IEEE J. Solid-State Circuits, Vol. 43, pp. 778–786, Apr., 2008.
  10. B. Chan, B. Oyama, C. Monier, and A. Guiterrez-Aiken, “An ultra-wideband 7-Bit 5-Gsps ADC implemented in submicron InP HBT technology,” IEEE J. Solid-State Circuits, Vol. 43, pp. 2187–2193, Oct., 2008.
  11. P. Schvan, J. Bach, C. Falt, P. Flemke, R. Gibbins, Y. Greshischev, N. Ben-Hamida, D. Pollex, J. Sitch, S.-C. Wang, and J. Woczanski, “A 24GS/s 6b ADC in 90nm CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 544–545, Feb., 2008.
  12. S. Shahramian, S. P. Voinigescu, and A. C. Carusone, “A 35-GS/s, 4-bit flash ADC with active data and clock distribution trees,” IEEE J. Solid-State Circuits, Vol. 44, pp. 1709–1720, June, 2009.
  13. J. Ryckaert, A. Geis, L. Bos, G. Vand Der Plas, and J. Craninckx, “A 6.1 GS/s 52.8 mW 43 dB DR 80 MHz Bandwidth 2.4 GHz RF Bandpass ∆∑ ADC in 40 nm CMOS,” Proc. of IEEE Radio Frequency Integrated Circ. Symp., Anaheim, CA, USA, pp. 443-446, May, 2010.
  14. Y. M. Greshishchev, J. Aguirre, M. Besson, R. Gibbins, C. Falt, P. Flemke, N. Ben-Hamida, D. Pollex, P. Schvan, and S.-C. Wang, “A 40GS/s 6b ADC in 65nm CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 390–391, Feb., 2010.
  15. M. K. Mayes, and S. W. Chin, “A 200 mW, 1 Msample/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller,” IEEE J. Solid-State Circuits, Vol. 31, pp. 1862-1872, Dec., 1996.
  16. R. J. van de Plassche, and H. J. Schouwenaars, “A monolithic 14 bit A/D converter,” IEEE J. Solid-State Circuits, Vol. SC-17, pp. 1112-1117, Dec., 1982.
  17. J.-Y. Wu, Z. Zhang, R. Subramoniam, and F. Maloberti, “A 107.4 dB SNR multi-bit sigma delta ADC with 1-ppm THD at 0.12 dB from full scale input,” IEEE J. Solid-State Circuits, Vol. 44, pp. 3060-3066, Nov., 2009.
  18. R. Payne, C. Sestok, W. Bright, M. El-Chammas, M. Corsi, D. Smith, and N. Tal, “A 12b 1GS/s SiGe BiCMOS Two-Way Time-Interleaved Pipeline ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, USA, pp. 182-184, Feb., 2011.
  19. AD7766, “24-Bit, 8.5 mW, 109 dB, 128 kSPS/64 kSPS/32 kSPS ADCs” Data Sheet, Analog Devices Inc., Aug, 2007.
  20. AD7986, “18-Bit, 2 MSPS PulSAR 15 mW ADC in LFCSP (QFN),” Data Sheet, Analog Devices Inc., Apr., 2009.
  21. MAX104, “+/-5V, 1Gsps, 8-bit ADC with on-chip 2.2GHz track/hold amplifier,” Data Sheet, Maxim Integrated Products Inc., Sept., 1999.
  22. R. C. Taft, P. A. Francese, M. R. Tursi, O. Hidri, A. MacKenzie, T. Hoehn, P. Schmitz, H. Werker, and A. Glenny, “A 1.8V 1.0GS/s 10b self-calibrating unified-folding-interpolating ADC with 9.1 ENOB at Nyquist frequency,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 78-79, Feb., 2009.