Tag Archives: scientific

NoMe TDC 2013


If you’re interested in Time-to-Digital Converters (TDC), and have been looking for a more dedicated event, you may want to check out the 2013 IEEE Nordic Mediterranean Workshop on Time to Digital Converters held in
Perugia, Italy, 3 October 2013.

You may still remember what I think about having data-converter conferences in Italy – it’s a fantastic idea. The food, the beautiful landscape, historic buildings and nice weather made me fall head over heels in love with the country. So check the conference site out to see if it’s something for you.

These conference snacks were served in Orvieto, but I’m sure that no one is going to starve in Perugia either … 😉

ADC Survey: Spring 2013 update on FOM

Winter seems to be super-glued to Sweden this year, so to illustrate “spring” I had to pick this photo from the archives.

Winter seems to be super-glued to Sweden this year, so to illustrate “spring” I had to pick this photo from the archives: Liverleaf (Hepatica Nobilis) in all its glory.

ADC FOM UPDATE: It’s now “post-ISSCC”, which is a more than sufficient reason to update the survey. If you were lucky enough to attend ISSCC this year, you may be familiar with the progress in A/D-converter figure-of-merit (FOM) since the Christmas 2012 Update. If not, I will summarize it here. This update also covers the most recent issues of IEEE Journal of Solid-State Circuits (JSSC), Transactions on Circuits and Systems pt. I and II, and ADC papers from ISOCC 2012. Unfortunately, the 2012 version of A-SSCC doesn’t seem to have made it into IEEE Xplore yet, so the 11 or so ADC papers that were published there will have to wait until next update. Even without the A-SCCC 2012, the survey now includes 4057 experimental data points extracted from 1810 scientific papers published between 1974 and Q1-2013.


Already from the paper titles in the ISSCC 2013 Advance Program, it was clear that the previous 2.8 fJ world record by Harpe et al. [1] wasn’t going to stand for long. Of the two papers reporting an improved Walden FOM, the 10-b SAR by Liou and Hsieh [2], National Tsing Hua University, Hsinchu, Taiwan, achieves an impressive 2.4 fJ. Nevertheless, Pieter Harpe and coauthors Cantatore and van Roermund from Eindhoven University of Technology, The Netherlands, keep the leader position through their new 10/12-b SAR [3], achieving 2.2 fJ in 12-b mode.

Clearly, both of the above designs are outstanding works. Something I particularly liked with the Harpe ADC was the elegant way they reduced the impact of comparator noise only for the decision(s) when it is really needed (i.e., when the comparator input is weak). Check it out, and enjoy the beauty of it all.

Another highlight is that Harpe et al. were able to set the new FOM world record and simultaneously push ENOB to 10.1 bits. Since the Walden FOM does not correctly model the energy vs. resolution trade-off for thermal noise limited designs, it is more difficult to achieve a good FOM the higher resolution you have. We’ll take a deeper look into that very soon in future posts. For now we can just conclude that the effort represented by their result is therefore even more admirable.

Additional observations

As observed in the Christmas 2012 Update, state-of-the-art Walden FOM is typically reported at lower-than-nominal supply voltages. This is true also for the present update. If you are aiming to win the FOM race you obviously need to make a really good design in the first place. Then, when you’re measuring, it seems that a good advice would be to sweep the VDD downwards, accept that the circuit becomes slower and noisier, and simply search for the VDD sweet spot where you get the best FOM to report.

Another striking feature is that sub-10fJ Walden FOM has so far been reported from only a handful of countries, of which The Netherlands and Taiwan currently seem to have the initiative. I will probably focus on this geographical aspect in a separate post, so I’ll just leave you with this teaser for now.

Thermal FOM

As in the previous update, no progress is reported beyond the Thermal FOM of 1.1 aJ reported by Xu [4], but for Nyquist ADCs, the Walden FOM winner above [3] is also the new Thermal FOM winner with a new world record of 2.0 aJ. So, double gold medals for Harpe, Cantatore and van Roermund from Eindhoven University of Technology. Excellent job!

I also want to mention that the design by Liou and Hsieh [2] – the silver medalists in the Walden FOM category above – also weigh in as the third best Thermal FOM ever reported for Nyquist ADCs.

There are a few more designs now becoming visible on my “sub-10aJ radar”. Of these, I’d like to point out the ring-amp based ADC by Hershberg et al. [5]. First of all it’s not a SAR. Among low-energy Nyquist ADCs, that’s unusual in itself. Secondly, the authors suggest that Ring Amp realization of ADCs could be a way to beat the noise-floor vs. technology scaling limits predicted for example by myself in [6]. And, as much as I like to be right in my predictions, I still prefer that I am wrong and the ADC field continue to evolve beyond all limits we can see today. So I hope they are right about the Ring Amp ADC, and will follow up with more experimental results to establish that once and for all.

Or … that someone else of you has something even better in your drawer.

Upcoming posts

Unless I get too fascinated with the geographic aspects of low-energy ADC research, the plan is to start looking at the energy vs. performance limits from a mostly empirical perspective. I hope to deliver something that is useful for those of you active in this race.


  1. P. Harpe, G. Dolmans, K. Philips, and H. de Groot, “A 0.7V 7-to-10bit 0-to-2MS/s Flexible SAR ADC for Ultra Low-Power Wireless Sensor Nodes,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Bordeaux, France, pp. 373–376, Sept., 2012.
  2. C.-Y. Liou, and C.-C. Hsieh, “A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with Charge-Average Switching DAC in 90nm CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, USA, pp. 280–281, Feb., 2013.
  3. P. Harpe, E. Cantatore, and A. van Roermund, “A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, USA, pp. 270–271, Feb., 2013.
  4. J. Xu, X. Wu, M. Zhao, R. Fan, H. Wang, X. Ma, and B. Liu, “Ultra Low-FOM High-Precision ΔΣ Modulators with Fully-Clocked SO and Zero Static Power Quantizers,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.
  5. B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U.-K. Moon, “Ring Amplifiers for Switched Capacitor Circuits,” IEEE J. Solid-State Circuits, Vol. 47, pp. 2928–2942, Dec., 2012.
  6. B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.

ADC Survey: Christmas 2012 update on FOM

ADC FOM UPDATE: I’ve understood that many Converter Passion readers are the very scientists who advance the state-of-the-art for A/D-converters. You are most certainly keeping a close eye on the progress yourselves. But in case you haven’t had time to scan the output of every major conference and top journal lately, this post will summarize the figure-of-merit (FOM) evolution since the Spring 2012 Update.

What’s new?

This update adds coverage for the 2012 versions of Symposium on VLSI Circuits, ESSCIRC and CICC. Also the most recent issues of IEEE Journal of Solid-State Circuits (JSSC), and Transactions on Circuits and Systems pt. I and II. A total of 64 new sources were added to the survey, so that it now includes 3917 experimental data points extracted from 1772 scientific papers published between 1974 and Oct/Dec 2012.


As mentioned in the previous update, the 4.4 fJ reported by van Elzakker et al. at ISSCC 2008 [1] has been an impressively persistent world record for “The FOM”

F_{A1} = \dfrac{P}{{2}^{ENOB}\times f_{s}}

It lasted for over four years until June 2012 until Tai et al [2] presented a 3.2 fJ SAR ADC at the IEEE Symposium for VLSI Circuits. Congratulations to the team from National Taiwan University, Taipei, Taiwan for their outstanding achievement. With their 0.35 V design, the NTU team were the new FOM champions between June and August 2012.

In September there was ESSCIRC. This year’s ESSCIRC had no less than four ADCs with a sub-10 fJ FOM [3]-[6]. No extra points for guessing the architecture – yes, they are all SAR. Among the four, the 2.8 fJ, 0.7 V, 7–10-b, flexible SAR by Harpe, et al. [3], is the new winner. The Eindhoven-based team behind the impressive world-record FOM are from the Holst Centre and Eindhoven University of Technology, The Netherlands. Excellent job, indeed! Many greetings from Converter Passion.

Beside the winners, all designs that achieved an FA1 < 10 fJ since the last update are listed below. Their combinations of {FA1, fs, ENOB, technology, VDDmax} are shown. In addition to all being variations of the SAR architecture, they are also close to the 9-b sweet spot for FA1, as predicted in “The path to a good A/D-converter FOM” and [7]. Except for the 7.07-b design by Yoshioka, et al. [6], they are all gathered within a 0.5-b slim interval centered just above 9-b. As explained in [7], this is not by accident.

Another clear trend is to operate the ADC at a lower-than-nominal supply voltage. As you can se from the table, the CMOS nodes range from 180 to 45 nm, but all six are run at low or ultra-low voltage. This is directly beneficial as it reduces the digital switching power. It is also likely to cause the converter to become limited by analog noise, which is pretty much a requirement when you’re aiming for energy-optimal operation.

FOM [fJ] Speed [S/s] ENOB Node [nm] VDD [V] 1st Author Ref
2.8 2M 9.31 90 0.7 Harpe [3]
3.2 100k 9.06 90 0.35 Tai [2]
3.9 2M 9.29 65 0.7 Yin [4]
4.5 1k 8.80 65 0.6 Zhang [5]
6.1 1.3M 7.07 45 0.4 Yoshioka [6]
8.0 200k 9.33 180 0.6 Huang [8]

What’s in the future?

It seems that a larger body of research efforts are now catching up with the rather extreme step taken by van Elzakker et al. The region below 10 fJ is rapidly becoming more densely populated. Within a six months period we saw two new world records, and with so much focus on this particular performance measure, we are likely to see more. In fact, judging from the titles in the ISSCC 2013 advance program, there are already two designs below 2.8 fJ lining up to be presented there. Perhaps more. Wish I could go there too.

Historically, the state-of-the-art FOM has mainly been reported in JSSC and at ISSCC, with the occasional publication at other conferences. As noted above, we can expect more to come out of ISSCC in the future, but ESSCIRC has clearly raised its profile with respect to ADC FOM in this millennium. Looking at the number of unique publications advancing the state-of-the-art FOM over time sorted by source publication, we get the “market share” of world records for each conference/journal, as shown in Fig. 1. Since the data between 2000 and 2012 consists of only 7 unique FOM advancements, we can’t be too sure about the trends. But it certainly makes ESSCIRC look good, doesn’t it?

Pie charts

Fig. 1. Where was the state-of-the-art FOM published? (a) Accumulated total (b) 1982–1999 (b) 2000–2012. [Click to enlarge]

Thermal FOM

As discussed in a previous post, the overall evolution of the “Thermal FOM”

F_{B1} = \dfrac{P}{{2}^{2\times ENOB}\times f_{s}}

over time has slowed down, and as explained in [9] it may not improve much over technology scaling. It is therefore no surprise that the overall FB1 remains unchanged at the 1.1 aJ reported by Xu [10].

Thermal FOM for Nyquist ADCs

New thermal-FOM champions for Nyquist converters are actually the same as the Walden-FOM winners above: First, the design by Tai et al. [2] nudged the previous 6.6 aJ record by Verbruggen et al. [11] down to 6.0 aJ. After a few months, Harpe et al. took the thermal FOM down to 4.4 aJ, which is the current world record.

Final words

All papers highlighted in this update represent considerable efforts and significant achievements with respect to energy efficiency. It was a joy reading them, and it will be exciting to see how far this evolution will take us.

To the blog readers that celebrate Christmas, I wish you a Merry one – to the rest, a Joyful Season. To all of us, a Happy New Year!

Next up is a book review, which I hope to post soon.

<- Previous FOM update


  1. M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.
  2. H.-Y. Tai, H.-W. Chen, and H.-S. Chen, “A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS,” Symp. VLSI Circ. Digest of Technical Papers, Honolulu, USA, pp. 92–93, June, 2012.
  3. P. Harpe, G. Dolmans, K. Philips, and H. de Groot, “A 0.7V 7-to-10bit 0-to-2MS/s Flexible SAR ADC for Ultra Low-Power Wireless Sensor Nodes,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Bordeaux, France, pp. 373–376, Sept., 2012.
  4. G. Yin, H.-G. Wei, U-F. Chio, S.-W. Sin, S.-P. U, Z. Wang, and R. P. Martins, “A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Bordeaux, France, pp. 377–380, Sept., 2012.
  5. D. Zhang, and A. Alvandpour, “A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Bordeaux, France, pp. 369–372, Sept., 2012.
  6. K. Yoshioka, A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with Wide Range Threshold Configuring Comparator,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Bordeaux, France, pp. 381–384, Sept., 2012.
  7. B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, June 2011. [PDF @ IMEKO]
  8. G.-Y. Huang, S.-J. Chang, C.-C. Liu, and Y.-Z. Lin, “A 1-μW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications,” IEEE J. Solid-State Circuits, Vol. 47, pp. 2783–2795, Nov., 2012.
  9. B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.
  10. J. Xu, X. Wu, M. Zhao, R. Fan, H. Wang, X. Ma, and B. Liu, “Ultra Low-FOM High-Precision ΔΣ Modulators with Fully-Clocked SO and Zero Static Power Quantizers,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.
  11. B. Verbruggen, M. Iriguchi, and J. Craninckx, “A 1.7mW 11b 250MS/s 2× Interleaved Fully Dynamic Pipelined SAR ADC in 40nm Digital CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 466–467, Feb., 2012.

A survey of ADC surveys

Figure 1. Accumulated publication count for scientifically reported ADC implementations in mainstream IEEE sources. The number of publications equivalent to 20% of total is indicated for reference.

SURVEYS GALORE: If the ten posts long A/D-converter survey just concluded did not fully satisfy your desire for scatter plots and tech trends, then this post will provide a list of prior ADC survey works as suggested “further reading”. In fact, I’d recommend everyone serious about data-converter technology trends to get hold of these documents. The list will also serve as a brief history of the ADC survey field. But first some thoughts on surveys:

Survey characteristics

When is it a “survey”? — I’m not going to spend too much energy on a stringent definition of a “survey”. My guideline is that a survey should be based on a significant amount of data, and that the visualization, discussion and interpretation of the data is the main work. Many scientific papers nowadays include a scatter plot that compares a particular design with 5–20 relevant prior efforts. While it’s a good idea to do so, these papers are not considered surveys in this context. Others use large amounts of empirical data to validate or derive a model, but the focus is more on the model.

What is “a significant amount of data”? — The size of the survey should be related to the total amount of data available at the time of the survey. A survey of 200 papers would have been exhaustive in 1990. Today it represents less than 12% of all scientific publications. The accumulated amount of scientific papers over time is shown in Fig. 1. While this is not the absolute total number of ADC publications, it covers the ADC implementations reported in nearly all journals and conferences central to the A/D-converter field, and shall for simplicity be referred to as the “total” amount here. The number of sources equivalent to 20% of the accumulated total at any given time is also shown in Fig. 1.

So, how much of the total do I need? Well, it depends on what you’re trying to do. When it comes to survey data, I’m a firm believer in “the more the merrier”, but there are tasks which can be done with a fairly small subset. For example, if you want to get an idea of the overall trend for one parameter vs. another or just make a quick sanity check.

Small subsets do have some limitations though. For the subset to function as a reasonably generic approximation of the exhaustive set, its data must span roughly the same chunk of parameter space, and have similar distribution of values in all dimensions. This is difficult to achieve unless you make a random sampling of the exhaustive set. A smaller set also risks running out of data, for example when dividing it further according to some parameter such as resolution or architecture.

How quickly will a survey become dated? — I really don’t know. I guess it depends on what you wish to study. But we can observe, as in Fig. 2, how the accumulated total at any given time relates to the overall total (here 1708 papers), and what percentage of currently available works were yet unpublished at any given time (e.g., at the end year of a particular survey). It is seen that approximately 50% of all currently available papers (~Q1-2012) were published in the last 8–8.5 years, i.e., after 2003, and almost 30% were not yet published in 2007. By the end of 1997, 70% of today’s body of empirical data was still unpublished.

You can use Fig. 2 to assess how old a survey can be before it’s no longer useful for your purpose. Can you make business decisions based on trend estimates where the most recent half of the data set is missing? Probably not. Most recent 30/20/10%? If so, you need a survey that’s less than approximately 4/3/1 years old.

It is clear that continuously updated surveys, such as Murmann’s, or the one used here at Converter Passion are preferable over single-shot attempts, since the former allows for continuously updated trend estimations.

Figure 2. Paper “yield”. The fraction of current total already published (blue) and yet to be published (red) at the end of any given year.

Known ADC surveys

Author Size Years Type What Ref
Walden 100 ≤ 1994 Both Perf. limits, FOM [1]
Walden 150 1978-1997 Both Perf. limits, FOM, jitter, evolution [2]
Merkel 150 1993-2002 Both Perf. limits, SFDR, power, VDD, scaling, device, arch. [3]
Le 1000 1983-2004 Parts Perf. limits, jitter, cost, arch., no. chan, N [4]
Walden 175 1978-2007 Both Update++ [5]
Walden n/a 1978-2008 Both Update [6]
Murmann ~260 1997-2008 Sci Perf. limits, VDD, scaling, FOM, evolution [7]
Jonsson 1400 1974-2010 Sci Perf., VDD, scaling, FOM, evolution [8]
Jonsson 1100 1976-2010 Sci Perf. & FOM vs. CMOS scaling, evolution [9]
Fuiano 5540 1970-2010 Sci Data-converters, research/patent correlation [10]
Jonsson 1400 1974-2010 Sci Energy/sample by arch [11]
Jonsson 1500 1974-2011 Sci Area eff by arch [12]
Murmann ~350 1997-2012 Sci Online survey data [13]
Jonsson 1700 1974-2012 Sci Perf., VDD, scaling, jitter, SFDR, FOM, evolution [14]

About the surveys


The “mother of all ADC surveys”, and the most frequently cited of all, is the pioneering work by Walden [2] where 150 scientific and commercial ADCs were analyzed, and performance trends were extracted. An earlier version was published already in 1994 [1], but this extended work became “The Walden Survey” to most of us. Although the 150 source documents originated from a mix of commercial and experimental designs, the Walden survey had a size equivalent to 30% of all scientific publications available at the time. The methods introduced in [2] are still useful, but Fig. 1 and Fig. 2 suggest that the trends extracted in [2] are unlikely to be valid and applicable today. At least they would have to be confirmed using more recent data. Two updated versions of the survey were published in 2008 – one covering 175 ADCs and data until 2007 [5], and one with an unspecified survey size and data until 2008 [6]. It is unclear how the 175 converters included in [5] were selected. During the time from Walden’s classic survey to 2007, the academic output alone generated another 715 new sources – commercial parts not counted. The +25 increase in source data therefore seems surprisingly incremental. Still, some of the results in [5] align very well with Converter Passion data, so apparently it was a carefully chosen subset.

Merkel & Wilson

Merkel and Wilson surveyed 150 commercial and scientific ADCs with specifications suitable for defense space applications [3]. Their data appear to span from 1993–2002, and the selection criteria for inclusion in the survey was a sampling rate fs ≥ 1 MS/s, and nominal resolution ≥ 12 bits. The paper does not reveal the mix between scientific papers and commercial parts, but gathering 150 sources must have been quite an effort by the authors. The total scientific output matching these specs and the time period is no more than 81 papers, and only 59 in the two sources (ISSCC, JSSC) the authors mention as primary. An additional minimum of 69–91 commercial parts must have been included to reach 150 sources. It is therefore assumed that the Merkel & Wilson data set was close to exhaustive for the spec range surveyed, and exhaustive data sets are always applauded here at Converter Passion.

The analysis and discussion itself is geared towards the stated application and focused on linearity (SFDR) to the extent that noise parameters are not treated at all. Power dissipation, supply voltage, speed, device type, scaling and architecture were observed.

Le, Rondeau, Reed & Bostian

An enormous data set, covering nearly 1000 commercial ADC parts from 1983–2004 was used in the survey by Le, Rondeau, Reed and Bostian [4]. As a comparison, the scientific output from the same years (not included in their survey) is 900 papers. The work is firmly rooted in the Walden tradition, but also considers parameters such as the number of channels per package and cost vs. performance. Additionally, the treatment separates the data by architecture, which adds an interesting extra dimension. Because of the larger volume and time span of the data set, part of the focus is to establish differences between this work and the classic Walden paper. Unfortunately, some exponentially improving parameters were plotted along linear axes, which makes many results from the survey difficult to see or interpret. Nevertheless, the contribution by Le et al. is a gigantic work and a key reference.


The survey by Murmann [7] is a significant recent contribution to the analysis of empirical performance data. It covers approximately 260 scientific ADCs reported 1997–2008 at the two conferences VLSI Circuit Symposium and ISSCC. The work analyzes ADC performance trends with a focus on energy per sample and signal-to-noise-and-distortion ratio (SNDR). The impact of process and voltage scaling is considered. If you don’t have this paper already, you should definitely head over to IEEE Xplore and get it right now.

Murmann’s survey has further benefits in that it is continuously updated and the data set is available online [13]. The latter opens up a lot of possibilities for anyone wishing to analyze the data in their own way, and makes the survey a very important contribution to the field. It currently includes around 350 sources.

Fuiano, Cagnazzo & Carbone

A rather different angle is taken in [10], where Fuiano, Cagnazzo and Carbone use survey data to analyze the correlation between scientific literature and patent activity. Compared to more “Waldenesque” surveys, this is a rather different animal. It nevertheless appeals to me as it illustrates an attempt to mine large amounts of survey data for something more unusual than ENOB, fs and FOM.


The ADMS Design data set used here at Converter Passion has also been used in five scientific papers, of which four are “surveys”:

  • ADC trends and performance evolution over time was analyzed in [8].
  • The impact of CMOS scaling on ADC performance was empirically analyzed in [9].
  • ADC architectures were compared with respect to energy efficiency in [11].
  • Area-efficiency of ADC architectures was surveyed in [12].

The largest survey for which this data set has been used so far is the recently published series of posts on A/D-converter performance evolution [14].

Other survey-related literature

A few other prior publications that are “survey-ish”, or otherwise use a large set of empirical data for their analysis are listed here:

  • Vogels and Gielen used a multidimensional regression fit to derive an ADC power dissipation model/FOM based on ≥ 70 empirical data points divided by architecture [15]. A similar approach was recently used by Verhelst and Murmann to analyze power dissipation and area vs. scaling based on Murmann’s data set [16] .
  • Sundström, Murmann, and Svensson derived theoretical power dissipation bounds in [17], and used the Murmann set to compare theory with empirical reality.
  • In [18], it was illustrated how the quality of a figure-of-merit (FOM) can be assessed by testing it against a large set of empirical data.

If you feel that I’ve left out any contributions that could have been mentioned in this post, just add a comment below.

See also …

ADC survey data

A/D-converter performance evolution

EveryNano Counts: “Those ADC Literature Surveys”


  1. R. H. Walden, “Analog-to-digital converter technology comparison,” in Proc. of GaAs IC Symp., pp. 228–231, Oct., 1994.
  2. R. H. Walden, “Analog-to-digital converter survey and analysis,” IEEE J. Selected Areas in Communications, no. 4, pp. 539–550, Apr. 1999.
  3. K. G. Merkel, and A. L. Wilson, “A survey of high performance analog-to-digital converters for defense space applications,” in Proc. IEEE Aerospace Conf., Big Sky, Montana, Mar. 2003, vol. 5, pp. 2415–2427.
  4. B. Le, T. W. Rondeau, J. H. Reed, and C. W. Bostian, “Analog-to-digital converters [A review of the past, present, and future],” IEEE Signal Processing Magazine, pp. 69–77, Nov. 2005.
  5. R. Walden, “Analog-to-digital conversion in the early twenty-first century,” Wiley Encyclopedia of Computer Science and Engineering, pp. 126–138, Wiley, 2008.
  6. R. H. Walden, “Analog-to-digital converters and associated IC technologies,” in Proc. Compound Semiconductor Integrated Circuits Symp., Monterey, Oct. 2008, pp. 1–2.
  7. B. Murmann, “A/D converter trends: Power dissipation, scaling and digitally assisted architectures,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 105–112, Sept., 2008.
  8. B. E. Jonsson, “A survey of A/D-converter performance evolution,” Proc. of IEEE Int. Conf. Electronics Circ. Syst. (ICECS), Athens, Greece, pp. 768–771, Dec., 2010.
  9. B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, Nov. 2010.
  10. F. Fuiano, L. Cagnazzo, and P. Carbone, “Data Converters: an Empirical Research on the Correlation between Scientific Literature and Patenting Activity,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June, 2011.
  11. B. E. Jonsson, “An empirical approach to finding energy efficient ADC architectures,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011.
  12. B. E. Jonsson, “Area Efficiency of ADC Architectures,” Proc. of Eur. Conf. Circuit Theory and Design (ECCTD), Linköping, Sweden, pp. 560–563, Aug., 2011.
  13. B. Murmann, “ADC Performance Survey 1997-2012,” [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html.
  14. B. E. Jonsson, “A/D-converter Performance Evolution,” Converter Passion, Aug., 2012, Available: https://converterpassion.wordpress.com/articles/ad-converter-performance-evolution/.
  15. M. Vogels, and G. Gielen, “Architectural Selection of A/D Converters,” Proc. of Des. Aut. Conf. (DAC), Anaheim, California, USA, pp. 974–977, June, 2003.
  16. M. Verhelst, and B. Murmann, “Area scaling analysis of CMOS ADCs,” El. Letters, Vol. 48, No. 6, pp. 315–315, Mar., 2012, IEE.
  17. T. Sundström, B. Murmann, and C. Svensson, “Power dissipation bounds for high-speed Nyquist analog-to-digital converters,” IEEE Trans. Circuits and Systems, pt. I, vol. 56, no. 3, pp. 509–518, Mar. 2009.
  18. B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011.

ADC performance evolution: Linearity (SFDR)

SFDR-vs-fin evolution

Figure 1. Evolution of SFDR-vs.-fin envelope for scientifically reported ADCs: Current state-of-the art is compared to state-of-the-art envelopes at 1990 (#) and 2000 (<).

LINEARITY TRENDS: After observing trends for technology scaling, voltage scaling, and noise, we have arrived at linearity. As far as the blogger is aware, there has been no large survey on A/D-converter linearity evolution published to this date, except for a recent work by Walden [1], where an “SFDR-bits” vs. fin scatter plot illustrates the state-of-the-art movement between 1999 and 2007 for the outermost corner/edge of the data, based on approximately 175 ADCs. In this post we will instead observe the migration of the entire envelope (state-of-the-art) for SFDR vs. input frequency (and sampling rate) in order to observe how SFDR evolved across multiple frequency ranges between 1990, 2000 and present (~Q1-2012). We will also slice through the data set, and specifically observe SFDR evolution at four very different speed grades of minimum sampling rate. The underlying data is from a survey of 1708 scientific ADC papers published between 1974 and Q1-2012.

ADC linearity trends: SFDR-vs-frequency envelope

While SNR, or an aggregate noise-and-distortion measure such as SNDR, is a sufficient measure of ADC performance for some applications, there are other applications where non-linear distortion is independently specified. Such applications include high-end audio and many wireless communication systems. Wireless communication systems often need to cope with the presence of a strong interferer in the form of a neighboring channel or carrier, while correctly interpreting a weak signal of interest. Without a sufficiently linear signal path, the interfering signal will generate harmonics or intermodulation products that may completely block the in-channel signal. The evolution of ADC linearity is therefore as important as the noise and ENOB evolution.

State-of-the-art envelopes for single-tone spurious-free dynamic range (SFDR) vs. input frequency fin and Nyquist sampling rate fs have been plotted in Fig. 1 and Fig. 2 respectively. Current state-of-the-art at ~Q1-2012 is compared to that of 1990 and 2000 in order to illustrate the evolution over all frequencies. Starting with the envelopes at 1990, the linearity vs. fin and fs is evenly distributed across almost straight lines representing the increasing difficulty to achieve high linearity as the input frequency and sampling rate is increased. The first of the two noticeable performance peaks in Fig. 1 coincide with the 20 kHz audio bandwidth, and the second peak is defined by video and instrumentation ADCs in the frequency range 10-100 MHz. It is evident from both plots that most of the progress from 1990 to the current state-of-the-art was achieved in the first decade 1990-2000 when SFDR vs. fin was improved by 20-40 dB across all input frequencies in the 100 kHz to 1GHz range, and SFDR vs. fs increased by 5-30 dB for the same range of sampling frequencies. Although state-of-the-art linearity has been increased by 5-10 dB over many segments of the frequency range during the last 11 years, Figs. 1 and 2 clearly shows that there has been a slowdown in the evolution of linearity over a broad range of frequencies and speed grades. One noticeable exception is the 30 dB performance lift in the 100-250 MS/s speed range, which reflects the specifications of the more recent wideband radio base-stations (RBS). It was concluded in a previous post that the evolution of communications standard requirements has been a strong driver for ADC jitter performance. Observing that the strongest push of the linearity envelopes also occurred at frequencies and sampling rates matching the specifications for wideband RBS, e.g., [2]-[5], it is concluded that communications applications have been a key driver for ADC linearity as well. This is also the conclusion of Walden in [1]. Another significant achievement during the last decade has been to improve performance at the high-frequency end of the spectrum, with sampling rates above 4 GS/s and input frequencies beyond 1 GHz [6]-[14]. Again, a similar observation is made in [1].

SFDR-vs-fs evolution

Figure 2. Evolution of SFDR-vs.-fs envelope for scientifically reported ADCs: Current state-of-the art is compared to state-of-the-art envelopes at 1990 (#) and 2000 (<).

ADC linearity trends: SFDR by speed grade

Figure 3 shows the evolution of peak SFDR at minimum speed grades of fs ≥ {10k, 1M, 100M, 1G} samples/s. The curves show the monotonically improving upper edge for each subset of survey data. What is included in each subset is defined by the four minimum sampling rate constraints. As in Fig. 1 and Fig. 2, the overall scatter is removed for readability.

My interpretation of Fig. 3 is as follows:

  • 1MS/s ADCs appear to have saturated at an SFDR of 108 dB [15], and have not improved since 1996.
  • 100 MS/s ADCs has slowed-down evolution beyond 100 dB to ~6 dB/decade or less. Current state-of-the-art is 102 dB SFDR [5].
  • At very low, and very high sampling rates there are no signs of saturation yet. For ADCs with fs ≥ 10 kS/s, there has been an almost constant progress of ~9dB/decade from 1992 [16] to 2009 [17].
  • ADCs with fs ≥ 1 GS/s are currently evolving at an accelerated rate of ~3 dB/year. If this rate is maintained, gigasample ADCs could go from 75 dB [18] to upwards of 100 dB SFDR by 2020.
  • The accelerated rate of evolution seen at different times for different speed grades may reflect how research activities migrate to higher and higher sampling rates depending on what applications are in focus. Previously more of a niche product, gigasample ADCs are now becoming a mainstream necessity.
SFDR evolution by speed grades

Figure 3. Scientifically reported ADC implementations: Peak SFDR evolution over time for minimum sampling rates of 10k (o), 1M (#), 100M (<), and 1GS/s (diamond).

Commercial ADC parts

Although not shown here, the results were also compared with the data from 595 commercially released ADC parts. Current state-of-the-art envelope for both sets align well across most of the speed range, with one significant exception: There are already commercial parts with significantly better SFDR than their scientific counterparts at 2 MSPS and below, e.g., AD7766 [19] and AD7986 [20]. Commercial ADCs appear to have evolved beyond their experimental siblings in later years within this speed segment(*).

Another difference is in the paths each subset has followed towards today’s (mostly similar) state-of-the-art. In the GSPS range there is for example MAX 104 [21], specifying 69 dB SFDR at fin = 125 MHz almost a decade before the scientific publication by Taft [22], while scientific efforts seem to have been ahead in other frequency ranges (e.g., below 2MS/s) during earlier years(*).

Linearity trends are therefore more difficult to interpret, and to some degree depend on what products were reported scientifically and not. Such dependency could not be observed for any noise-related parameter analyzed in this series of posts.

(*) Please note that these are only my best guesstimates, as the commercial data set (although large) is not as exhaustive as that for scientific ADCs.

In the next post I plan to review the simultaneous evolution of {ENOB, fs}. Subscribe to the blog, and you won’t miss it.

See also …

ADC performance evolution: Thermal noise

ADC performance evolution: Jitter

ADC performance evolution: Relative noise floor

ADC performance evolution: Low-voltage operation – part 1

ADC performance evolution: Low-voltage operation – part 2

ADC survey data


  1. R. Walden, “Analog-to-digital conversion in the early twenty-first century,” Wiley Encyclopedia of Computer Science and Engineering, pp. 126–138, Wiley, 2008.
  2. A. Namdar, and B. H. Leung, “A 400MHz 12b 18mW IF digitizer with mixer inside a ΣΔ modulator loop,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 62–63, Feb., 1999.
  3. A. M. A. Ali, C. Dillon, R. Sneed, A. S. Morgan, S. Bardsley, J. Kornblum, and L. Wu, “A 14-bit 125 MS/s IF/RF sampling pipelined ADC with 100 dB SFDR and 50 fs jitter,” IEEE J. Solid-State Circuits, Vol. 41, pp. 1846–1855, Aug, 2006.
  4. A. M. A. Ali, A. Morgan, C. Dillon, G. Patterson, S. Puckett, P. Bhorashkar, H. Dinc, M. Hensley, R. Stop, S. Bardsley, D. Lattimore, J. Bray, C. Speir, and R. Sneed, “A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration,” IEEE J. Solid-State Circuits, Vol. 45, pp. 2602-2612, Dec., 2010.
  5. R. Payne, M. Corsi, D. Smith, T.-L. Hsieh, and S. Kaylor, “A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC With 100 dBFS SFDR,” IEEE J. Solid-State Circuits, Vol. 45, pp. 2613-2622, Dec., 2010.
  6. K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernilo, C. Tan, and A. Montijo, “A 20GS/s 8b ADC with a 1MB memory in 0.18μm CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 318–319, Feb., 2003.
  7. W. Cheng, W. Ali, M.-J. Choi, K. Liu, T. Tat, D. Devendorf, L. Linder, and R. Stevens, “A 3b 40GS/s ADC-DAC in 0.12μm SiGe,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 262–263, Feb., 2004.
  8. L. Y. Nathawad, R. Urata, B. A. Wooley, and D. A. B. Miller, “A 20GHz bandwidth, 4b photoconductive-sampling time-interleaved CMOS ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 320–321, Feb., 2003.
  9. S. M. Louwsma, A. J. M. van Tuijl, M. Vertregt, and B. Nauta, “A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS,” IEEE J. Solid-State Circuits, Vol. 43, pp. 778–786, Apr., 2008.
  10. B. Chan, B. Oyama, C. Monier, and A. Guiterrez-Aiken, “An ultra-wideband 7-Bit 5-Gsps ADC implemented in submicron InP HBT technology,” IEEE J. Solid-State Circuits, Vol. 43, pp. 2187–2193, Oct., 2008.
  11. P. Schvan, J. Bach, C. Falt, P. Flemke, R. Gibbins, Y. Greshischev, N. Ben-Hamida, D. Pollex, J. Sitch, S.-C. Wang, and J. Woczanski, “A 24GS/s 6b ADC in 90nm CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 544–545, Feb., 2008.
  12. S. Shahramian, S. P. Voinigescu, and A. C. Carusone, “A 35-GS/s, 4-bit flash ADC with active data and clock distribution trees,” IEEE J. Solid-State Circuits, Vol. 44, pp. 1709–1720, June, 2009.
  13. J. Ryckaert, A. Geis, L. Bos, G. Vand Der Plas, and J. Craninckx, “A 6.1 GS/s 52.8 mW 43 dB DR 80 MHz Bandwidth 2.4 GHz RF Bandpass ∆∑ ADC in 40 nm CMOS,” Proc. of IEEE Radio Frequency Integrated Circ. Symp., Anaheim, CA, USA, pp. 443-446, May, 2010.
  14. Y. M. Greshishchev, J. Aguirre, M. Besson, R. Gibbins, C. Falt, P. Flemke, N. Ben-Hamida, D. Pollex, P. Schvan, and S.-C. Wang, “A 40GS/s 6b ADC in 65nm CMOS,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 390–391, Feb., 2010.
  15. M. K. Mayes, and S. W. Chin, “A 200 mW, 1 Msample/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller,” IEEE J. Solid-State Circuits, Vol. 31, pp. 1862-1872, Dec., 1996.
  16. R. J. van de Plassche, and H. J. Schouwenaars, “A monolithic 14 bit A/D converter,” IEEE J. Solid-State Circuits, Vol. SC-17, pp. 1112-1117, Dec., 1982.
  17. J.-Y. Wu, Z. Zhang, R. Subramoniam, and F. Maloberti, “A 107.4 dB SNR multi-bit sigma delta ADC with 1-ppm THD at 0.12 dB from full scale input,” IEEE J. Solid-State Circuits, Vol. 44, pp. 3060-3066, Nov., 2009.
  18. R. Payne, C. Sestok, W. Bright, M. El-Chammas, M. Corsi, D. Smith, and N. Tal, “A 12b 1GS/s SiGe BiCMOS Two-Way Time-Interleaved Pipeline ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, USA, pp. 182-184, Feb., 2011.
  19. AD7766, “24-Bit, 8.5 mW, 109 dB, 128 kSPS/64 kSPS/32 kSPS ADCs” Data Sheet, Analog Devices Inc., Aug, 2007.
  20. AD7986, “18-Bit, 2 MSPS PulSAR 15 mW ADC in LFCSP (QFN),” Data Sheet, Analog Devices Inc., Apr., 2009.
  21. MAX104, “+/-5V, 1Gsps, 8-bit ADC with on-chip 2.2GHz track/hold amplifier,” Data Sheet, Maxim Integrated Products Inc., Sept., 1999.
  22. R. C. Taft, P. A. Francese, M. R. Tursi, O. Hidri, A. MacKenzie, T. Hoehn, P. Schmitz, H. Werker, and A. Glenny, “A 1.8V 1.0GS/s 10b self-calibrating unified-folding-interpolating ADC with 9.1 ENOB at Nyquist frequency,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 78-79, Feb., 2009.