Tag Archives: technology

New minor revision: A/D-converter performance evolution (v1.1)


T13001-ThumbNote that the recently released A/D-converter performance evolution “eBook”/PDF, has been incremented to v1.1 due to a mistake with Figure 6.3. The latest release can always be reached from the Document Download page. If you pass links around, be sure to link to that page instead of any direct link to a specific release.

My sincere apologies to the 38 readers who downloaded the document during the first hours.

Now as a free eBook/PDF: A/D-converter performance evolution


Updated (see below)!

I’m happy to see that the “A/D-converter performance evolutionarticle has become the most popular content on Converter Passion. There’s a huge amount of research work put into those ten posts, so I’m glad you liked it.

T13001-ThumbBut even the most die-hard fan of scatter plots and performance trend estimates may find it tiresome to have to click their way through the ten blog posts.  I even feel a bit lost myself from time to time. For your convenience (and mine too), I have therefore made the whole lot available as an “eBook”/PDF, which you can download here (4.8MB). It’s an almost exact replica of the original on-line content, so if you’ve read the original Converter Passion article there’s nothing new here. But it’s likely you find the format much easier to read. I certainly do.

If you’re working with ADCs, you have probably already clicked the link – it’s an absolute no-brainer: A 50-page fully functional PDF with 44 pages of content, 24 illustrations and 92 references. All for free.

Happy reading!

Update 2013-01-07: My sincere apologies to the 40 or so that have downloaded it already, but there was a bug with Fig. 6.3 (it was 6.2 duplicated). The correct graph has now been inserted in v1.1. of the document. Many thanks to EJ & Henk at Catena!

A survey of ADC surveys


Figure 1. Accumulated publication count for scientifically reported ADC implementations in mainstream IEEE sources. The number of publications equivalent to 20% of total is indicated for reference.

SURVEYS GALORE: If the ten posts long A/D-converter survey just concluded did not fully satisfy your desire for scatter plots and tech trends, then this post will provide a list of prior ADC survey works as suggested “further reading”. In fact, I’d recommend everyone serious about data-converter technology trends to get hold of these documents. The list will also serve as a brief history of the ADC survey field. But first some thoughts on surveys:

Survey characteristics

When is it a “survey”? — I’m not going to spend too much energy on a stringent definition of a “survey”. My guideline is that a survey should be based on a significant amount of data, and that the visualization, discussion and interpretation of the data is the main work. Many scientific papers nowadays include a scatter plot that compares a particular design with 5–20 relevant prior efforts. While it’s a good idea to do so, these papers are not considered surveys in this context. Others use large amounts of empirical data to validate or derive a model, but the focus is more on the model.

What is “a significant amount of data”? — The size of the survey should be related to the total amount of data available at the time of the survey. A survey of 200 papers would have been exhaustive in 1990. Today it represents less than 12% of all scientific publications. The accumulated amount of scientific papers over time is shown in Fig. 1. While this is not the absolute total number of ADC publications, it covers the ADC implementations reported in nearly all journals and conferences central to the A/D-converter field, and shall for simplicity be referred to as the “total” amount here. The number of sources equivalent to 20% of the accumulated total at any given time is also shown in Fig. 1.

So, how much of the total do I need? Well, it depends on what you’re trying to do. When it comes to survey data, I’m a firm believer in “the more the merrier”, but there are tasks which can be done with a fairly small subset. For example, if you want to get an idea of the overall trend for one parameter vs. another or just make a quick sanity check.

Small subsets do have some limitations though. For the subset to function as a reasonably generic approximation of the exhaustive set, its data must span roughly the same chunk of parameter space, and have similar distribution of values in all dimensions. This is difficult to achieve unless you make a random sampling of the exhaustive set. A smaller set also risks running out of data, for example when dividing it further according to some parameter such as resolution or architecture.

How quickly will a survey become dated? — I really don’t know. I guess it depends on what you wish to study. But we can observe, as in Fig. 2, how the accumulated total at any given time relates to the overall total (here 1708 papers), and what percentage of currently available works were yet unpublished at any given time (e.g., at the end year of a particular survey). It is seen that approximately 50% of all currently available papers (~Q1-2012) were published in the last 8–8.5 years, i.e., after 2003, and almost 30% were not yet published in 2007. By the end of 1997, 70% of today’s body of empirical data was still unpublished.

You can use Fig. 2 to assess how old a survey can be before it’s no longer useful for your purpose. Can you make business decisions based on trend estimates where the most recent half of the data set is missing? Probably not. Most recent 30/20/10%? If so, you need a survey that’s less than approximately 4/3/1 years old.

It is clear that continuously updated surveys, such as Murmann’s, or the one used here at Converter Passion are preferable over single-shot attempts, since the former allows for continuously updated trend estimations.

Figure 2. Paper “yield”. The fraction of current total already published (blue) and yet to be published (red) at the end of any given year.

Known ADC surveys

Author Size Years Type What Ref
Walden 100 ≤ 1994 Both Perf. limits, FOM [1]
Walden 150 1978-1997 Both Perf. limits, FOM, jitter, evolution [2]
Merkel 150 1993-2002 Both Perf. limits, SFDR, power, VDD, scaling, device, arch. [3]
Le 1000 1983-2004 Parts Perf. limits, jitter, cost, arch., no. chan, N [4]
Walden 175 1978-2007 Both Update++ [5]
Walden n/a 1978-2008 Both Update [6]
Murmann ~260 1997-2008 Sci Perf. limits, VDD, scaling, FOM, evolution [7]
Jonsson 1400 1974-2010 Sci Perf., VDD, scaling, FOM, evolution [8]
Jonsson 1100 1976-2010 Sci Perf. & FOM vs. CMOS scaling, evolution [9]
Fuiano 5540 1970-2010 Sci Data-converters, research/patent correlation [10]
Jonsson 1400 1974-2010 Sci Energy/sample by arch [11]
Jonsson 1500 1974-2011 Sci Area eff by arch [12]
Murmann ~350 1997-2012 Sci Online survey data [13]
Jonsson 1700 1974-2012 Sci Perf., VDD, scaling, jitter, SFDR, FOM, evolution [14]

About the surveys

Walden

The “mother of all ADC surveys”, and the most frequently cited of all, is the pioneering work by Walden [2] where 150 scientific and commercial ADCs were analyzed, and performance trends were extracted. An earlier version was published already in 1994 [1], but this extended work became “The Walden Survey” to most of us. Although the 150 source documents originated from a mix of commercial and experimental designs, the Walden survey had a size equivalent to 30% of all scientific publications available at the time. The methods introduced in [2] are still useful, but Fig. 1 and Fig. 2 suggest that the trends extracted in [2] are unlikely to be valid and applicable today. At least they would have to be confirmed using more recent data. Two updated versions of the survey were published in 2008 – one covering 175 ADCs and data until 2007 [5], and one with an unspecified survey size and data until 2008 [6]. It is unclear how the 175 converters included in [5] were selected. During the time from Walden’s classic survey to 2007, the academic output alone generated another 715 new sources – commercial parts not counted. The +25 increase in source data therefore seems surprisingly incremental. Still, some of the results in [5] align very well with Converter Passion data, so apparently it was a carefully chosen subset.

Merkel & Wilson

Merkel and Wilson surveyed 150 commercial and scientific ADCs with specifications suitable for defense space applications [3]. Their data appear to span from 1993–2002, and the selection criteria for inclusion in the survey was a sampling rate fs ≥ 1 MS/s, and nominal resolution ≥ 12 bits. The paper does not reveal the mix between scientific papers and commercial parts, but gathering 150 sources must have been quite an effort by the authors. The total scientific output matching these specs and the time period is no more than 81 papers, and only 59 in the two sources (ISSCC, JSSC) the authors mention as primary. An additional minimum of 69–91 commercial parts must have been included to reach 150 sources. It is therefore assumed that the Merkel & Wilson data set was close to exhaustive for the spec range surveyed, and exhaustive data sets are always applauded here at Converter Passion.

The analysis and discussion itself is geared towards the stated application and focused on linearity (SFDR) to the extent that noise parameters are not treated at all. Power dissipation, supply voltage, speed, device type, scaling and architecture were observed.

Le, Rondeau, Reed & Bostian

An enormous data set, covering nearly 1000 commercial ADC parts from 1983–2004 was used in the survey by Le, Rondeau, Reed and Bostian [4]. As a comparison, the scientific output from the same years (not included in their survey) is 900 papers. The work is firmly rooted in the Walden tradition, but also considers parameters such as the number of channels per package and cost vs. performance. Additionally, the treatment separates the data by architecture, which adds an interesting extra dimension. Because of the larger volume and time span of the data set, part of the focus is to establish differences between this work and the classic Walden paper. Unfortunately, some exponentially improving parameters were plotted along linear axes, which makes many results from the survey difficult to see or interpret. Nevertheless, the contribution by Le et al. is a gigantic work and a key reference.

Murmann

The survey by Murmann [7] is a significant recent contribution to the analysis of empirical performance data. It covers approximately 260 scientific ADCs reported 1997–2008 at the two conferences VLSI Circuit Symposium and ISSCC. The work analyzes ADC performance trends with a focus on energy per sample and signal-to-noise-and-distortion ratio (SNDR). The impact of process and voltage scaling is considered. If you don’t have this paper already, you should definitely head over to IEEE Xplore and get it right now.

Murmann’s survey has further benefits in that it is continuously updated and the data set is available online [13]. The latter opens up a lot of possibilities for anyone wishing to analyze the data in their own way, and makes the survey a very important contribution to the field. It currently includes around 350 sources.

Fuiano, Cagnazzo & Carbone

A rather different angle is taken in [10], where Fuiano, Cagnazzo and Carbone use survey data to analyze the correlation between scientific literature and patent activity. Compared to more “Waldenesque” surveys, this is a rather different animal. It nevertheless appeals to me as it illustrates an attempt to mine large amounts of survey data for something more unusual than ENOB, fs and FOM.

Jonsson

The ADMS Design data set used here at Converter Passion has also been used in five scientific papers, of which four are “surveys”:

  • ADC trends and performance evolution over time was analyzed in [8].
  • The impact of CMOS scaling on ADC performance was empirically analyzed in [9].
  • ADC architectures were compared with respect to energy efficiency in [11].
  • Area-efficiency of ADC architectures was surveyed in [12].

The largest survey for which this data set has been used so far is the recently published series of posts on A/D-converter performance evolution [14].

Other survey-related literature

A few other prior publications that are “survey-ish”, or otherwise use a large set of empirical data for their analysis are listed here:

  • Vogels and Gielen used a multidimensional regression fit to derive an ADC power dissipation model/FOM based on ≥ 70 empirical data points divided by architecture [15]. A similar approach was recently used by Verhelst and Murmann to analyze power dissipation and area vs. scaling based on Murmann’s data set [16] .
  • Sundström, Murmann, and Svensson derived theoretical power dissipation bounds in [17], and used the Murmann set to compare theory with empirical reality.
  • In [18], it was illustrated how the quality of a figure-of-merit (FOM) can be assessed by testing it against a large set of empirical data.

If you feel that I’ve left out any contributions that could have been mentioned in this post, just add a comment below.

See also …

ADC survey data

A/D-converter performance evolution

EveryNano Counts: “Those ADC Literature Surveys”

References

  1. R. H. Walden, “Analog-to-digital converter technology comparison,” in Proc. of GaAs IC Symp., pp. 228–231, Oct., 1994.
  2. R. H. Walden, “Analog-to-digital converter survey and analysis,” IEEE J. Selected Areas in Communications, no. 4, pp. 539–550, Apr. 1999.
  3. K. G. Merkel, and A. L. Wilson, “A survey of high performance analog-to-digital converters for defense space applications,” in Proc. IEEE Aerospace Conf., Big Sky, Montana, Mar. 2003, vol. 5, pp. 2415–2427.
  4. B. Le, T. W. Rondeau, J. H. Reed, and C. W. Bostian, “Analog-to-digital converters [A review of the past, present, and future],” IEEE Signal Processing Magazine, pp. 69–77, Nov. 2005.
  5. R. Walden, “Analog-to-digital conversion in the early twenty-first century,” Wiley Encyclopedia of Computer Science and Engineering, pp. 126–138, Wiley, 2008.
  6. R. H. Walden, “Analog-to-digital converters and associated IC technologies,” in Proc. Compound Semiconductor Integrated Circuits Symp., Monterey, Oct. 2008, pp. 1–2.
  7. B. Murmann, “A/D converter trends: Power dissipation, scaling and digitally assisted architectures,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 105–112, Sept., 2008.
  8. B. E. Jonsson, “A survey of A/D-converter performance evolution,” Proc. of IEEE Int. Conf. Electronics Circ. Syst. (ICECS), Athens, Greece, pp. 768–771, Dec., 2010.
  9. B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, Nov. 2010.
  10. F. Fuiano, L. Cagnazzo, and P. Carbone, “Data Converters: an Empirical Research on the Correlation between Scientific Literature and Patenting Activity,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June, 2011.
  11. B. E. Jonsson, “An empirical approach to finding energy efficient ADC architectures,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011.
  12. B. E. Jonsson, “Area Efficiency of ADC Architectures,” Proc. of Eur. Conf. Circuit Theory and Design (ECCTD), Linköping, Sweden, pp. 560–563, Aug., 2011.
  13. B. Murmann, “ADC Performance Survey 1997-2012,” [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html.
  14. B. E. Jonsson, “A/D-converter Performance Evolution,” Converter Passion, Aug., 2012, Available: https://converterpassion.wordpress.com/articles/ad-converter-performance-evolution/.
  15. M. Vogels, and G. Gielen, “Architectural Selection of A/D Converters,” Proc. of Des. Aut. Conf. (DAC), Anaheim, California, USA, pp. 974–977, June, 2003.
  16. M. Verhelst, and B. Murmann, “Area scaling analysis of CMOS ADCs,” El. Letters, Vol. 48, No. 6, pp. 315–315, Mar., 2012, IEE.
  17. T. Sundström, B. Murmann, and C. Svensson, “Power dissipation bounds for high-speed Nyquist analog-to-digital converters,” IEEE Trans. Circuits and Systems, pt. I, vol. 56, no. 3, pp. 509–518, Mar. 2009.
  18. B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011.

ADC performance evolution: Low-voltage operation – part 2


VDD evolution over time (scatterplot)

Fig. 1. Supply voltages used for scientifically reported CMOS ADCs over time. Data points representing the evolution of low-voltage state-of-the-art have been highlighted. Trend line fit to 1985-2007 data.

LOW-VOLTAGE EVOLUTION TRENDS: In part 1 of the low-voltage ADC series of posts, we observed the trends for supply voltage (VDD) vs. process scaling (L). In this second post we will complete the picture by looking at VDD trends over time. The timing for introduction of new process technology, and the nominal supply voltage for future nodes, are reasonably well-defined through the continuously updated International Technology Roadmap for Semiconductors (ITRS) [1], but at least two ADC-related aspects are not controlled by the ITRS scaling roadmap:

  • The rate at which mainstream ADC research activities will migrate to newer CMOS technology.
  • To what extent the ADC research community will attempt to push the envelope with respect to ultra-low voltage operation.

Regarding the former, it was observed in a previous post that the number of early adopters for each node is very small. In any year, the absolute majority of experimental ADCs have so far been implemented in technology being 2–5 generations behind the scaling front. How the “mainstream” will behave in the future is next to impossible to predict, as it is influenced by future industrial needs, research grant policies, research community group dynamics, journal and conference publication targets, as well as many other hard and soft parameters of which we know very little today.

The latter depends on a handful of pioneers choosing to explore the outer limits of ultra-low voltage ADC operation. It was seen in part 1 that there have been rather few attempts to push in this direction, which reveals that only a few groups have historically chosen this focus. If no one decides to have a shot at the current world record – the 0.2 V, VCO-based ∑-∆ modulator presented by Wismar et al. in [2] – we may never see it nudged.

It is therefore very difficult to predict the future VDD trends for analog-to-digital converters, both with respect to the ultra-low voltage state-of-the-art, and the mainstream supply voltage. What we can do, however, is to observe historical trends and use them as a reference.

Observation of ADC supply voltage trends

Figure 1 shows the voltage supplies reported for CMOS A/D-converters reported in scientific publications until Q1-2012. The graph shows the highest supply voltage applied to the circuit. It means that, if a circuit used several independent supplies, then VDD = max(VDD1, VDD2, …, VDDn), so that true low-voltage operation is promoted. The evolution of low-voltage state-of-the-art has been highlighted.

A similar graph in [3] shows data for all ADCs (CMOS, as well as bipolar and BiCMOS) but with data only to Q1-2010. Focusing on CMOS, and adding two more years of empirical data yields a different scatter. Nevertheless, the low-voltage state-of-the-art sequence here is nearly identical to that in [3] because the global state-of-the-art  almost completely coincides with CMOS ADCs, and also did not improve since 2006. As observed in [3], the lowest reported VDD remained unchanged at 5 V until 1985, after which it started to follow a noisy but distinct scaling trend for 20 years. Fitting to the state-of-the-art data from 1985–2007, yields that the lowest reported VDD was scaled by ~2× every five years during this period.

Figure 2 shows the distribution of scientific ADC implementations over supply voltage and publication year as a contour plot. The state-of-the-art data points and trend fit from Fig. 1 have been superimposed for reference. Just as in part 1, manually selected bin centers and non-linear contour levels have been used in order to render a meaningful and readable (but simplified) plot. The main purpose is to illustrate the difference between mainstream VDD and state-of-the-art low-voltage operation each year. It is observed that:

  • Mainstream focus remained at 5 V for over 20 years.
  • The state-of-the-art VDD scaling front started to go below 5 V around 12–15 years before any noticeable change in the mainstream focus.
  • The low-voltage scaling front appears to be approximately 5–6× below, and 10–15 years ahead of the mainstream VDD for each year.
  • Supply voltages from 5 V and down seem to have an extremely long lifetime in publications.

What do you observe?

Distribution of VDD over time (contour plot)

Figure 2. Voltage supplies used for scientific ADCs over time. Color represents number of publications. The low-voltage state-of-the-art data points are superimposed along with a scaling trend estimated from 1985–2007 data.

Future VDD scaling for ADCs

I’m very aware that there are good reasons why ultra-low VDD scaling may not be able go much further, so please note that I’m not saying here that it will. Perhaps it is physically impossible, or functionally meaningless to go significantly further than the 200 mV operation achieved by Wismar, et al. On the other hand, I’m old enough to have heard one “hard” limit after another being suggested for MOST scaling, and we’re still scaling them. So, let’s just see where we would end up if it should turn out to be possible also for the voltage supply:

If the current trend for ultra-low voltage ADCs should be maintained, the low-voltage pioneers would have to publish ADCs according to the following approximate schedule:

Year VDD
2015 73 mV
2020 36 mV
2025 18 mV

Again, I’m not saying that it will happen. But I still found it interesting to see what kind of supplies the historical trend is projecting towards. Does anyone dare to predict a hard limit for A/D-converter supply voltage? Do you believe we will ever see an ADC operating at 73 mV? Is 36 mV impossible? What are the possibilities in context of the impossibilities?

In case anyone wish to make their own projections, the trend fit expression is:

VDD = {10}^{-0.061011\times year + 121.7998}

See also …

ADC performance evolution: Low-voltage operation – part 1

ADC research trends: CMOS node adoption

ADC research trends: Migration to CMOS

ADC Survey Data

References

[1] International Technology Roadmap for Semiconductors (ITRS), 2011 Edition [Online]. Available: http://www.itrs.net

[2] U. Wismar, D. Wisland, and P. Andreani, “A 0.2V 0.44µW 20 kHz analog to digital ∑∆ modulator with 57 fJ/conversion FoM”, Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Montreux, Switzerland, pp. 187-190, Sept., 2006.

[3] B. E. Jonsson, “A survey of A/D-converter performance evolution,” Proc. of IEEE Int. Conf. Electronics Circ. Syst. (ICECS), Athens, Greece, pp. 768–771, Dec., 2010.

ADC performance evolution: Low-voltage operation – part 1


Figure 1. Two-dimensional view of CMOS scaling: Channel length and VDD.

EMBRACING LOW VOLTAGE OPERATION: As analog-to-digital converter implementations migrate to scaled-down CMOS technologies, they also face the inevitable downscaling of supply voltages (VDD), and hence signal swing [1]. A signal chain with a weak signal is more likely to suffer from noise than one with a strong signal. The scaling trends for VDD are therefore important as a background to the A/D-converter noise performance trends that will be treated in a few upcoming posts. There are also other reasons for a circuit designer to keep an eye on the evolution of supply voltage, such as the considerable challenges for high-gain OP-amp design or sampling linearity under low-voltage operation, so I hope you’ll find this post useful even on its own.

Voltage scaling: The stragglers, the mainstream, and the pioneers

Contrary to the minimum channel length (L), we can choose to go lower than the nominal supply voltage specified for a process. Possibly at our own risk, but at least it can be done. It has therefore been possible to scale VDD “ahead” of the node you actually use. Unless you have direct access to a semiconductor fab, you can’t do that with respect to L. This degree of freedom – at least for experimental ADC designs – has lead to the situation illustrated by Fig. 1:

  • Some (or as we shall see below, most) designs use the nominal supply voltage recommended for any given CMOS node.
  • Others may use the same node, but the design is not “fully scaled”. It relies on higher-than-nominal VDD, and possibly optional process steps that effectively recreate older and less scaled device technology as well.
  • A third category not only embraces the full scaling, but actually use a more aggressive scaling of supply voltages. These are the low-voltage pioneers.

This post will observe how supply voltage distribute over CMOS node for scientifically reported ADCs, and attempt to extract evolution trends and trajectories for VDD vs. L.

ADC supply voltage vs. CMOS node

As pointed out in [2], the reported supply voltage can vary as much as one order of magnitude within the same node for scientific A/D-converters. This is illustrated by the scatter plot of {L, VDD} for the entire CMOS ADC data set in Fig. 2. The VDD used in the plot is the highest supply voltage applied to each ADC, and the evolution of low-voltage state-of-the-art over CMOS nodes has been highlighted. Wismar, et al., reported a 90 nm VCO-based ∆-∑ modulator implementation running at 0.2 V supply voltage (operational @ 0.18 V), which is the lowest VDD published to this date [3].

Note that Fig. 2 differs form a similar graph in [2] in that the graph here is based on two more years of empirical data, and the plot in [2] shows the lowest VDD applied to each design instead of the highest. Also, the trajectory for the de facto nominal supply voltage vs. CMOS node is overlaid in Fig. 2. It is not necessarily the “official” VDD, but instead it was derived from the supply used by the majority of designs reported for each node. For nearly all nodes, the choice was abundantly clear. In 65 and 90 nm, however, there were significant subsets of designs using 1 V instead of the 1.2 V that was used by the majority.

Starting at 1.2 µm, the ultra-low voltage state-of-the-art appears to have followed a distinct trend of evolving as approximately one fifth of the nominal VDD. Because of the slowdown in nominal VDD scaling, that trend still holds in relation to the 0.2 V reported by Wismar.

VDD vs. CMOS node (scatter plot)

Figure 2. Supply voltages used for scientific ADCs vs. CMOS node. The low-voltage state-of-the-art data points have been highlighted, and the nominal/majority VDD trajectory superimposed.

Although the scatter in Fig. 2 shows all reported combinations of {L, VDD}, it does not reveal the distribution across scientific ADC papers. This is done in Fig. 3, where color contours represent the number of papers falling into a certain two-dimensional histogram bin. The bins used in this plot have been selected manually in order to create a meaningful, yet readable plot, so that bin centers align with major nodes on the L axis, and the most frequently used or otherwise interesting values on the VDD-axis. Furthermore, a non-linear, truncated, ad hoc mapping of contour levels was applied to handle the steep peeks at certain bins while still retaining visibility of all non-zero bins. The contours thus yield a simplified view of the actual distribution, and cannot be used to derive the actual bin counts or exact distribution. For completeness, Fig. 4 shows the full distribution of all unique combinations of {L, VDD} reported for scientific ADC implementations until Q1-2012.

Figures 3 and 4 show that the vast majority of experimental ADCs reported in scientific papers use the nominal supply voltage for each CMOS node, even if there is a large spread of actual VDD values used in each node. The variation extends significantly below and above the nominal values. We can also observe that the scaling rate for nominal supply voltage with CMOS node appears to have leveled out after 130 nm. Projected VDD for future nodes are found in [1].

In part 2, we will look at the trends for VDD over time.

VDD vs. CMOS node (contour plot)

Figure 3. Distribution of supply voltage used for scientific ADCs vs. CMOS node. Color contours indicate density of publications. The low-voltage state-of-the-art data points are superimposed along with the nominal VDD trajectory.

Figure 4. Distribution of all unique combinations of VDD and L (node) reported for CMOS ADC implementations in scientific papers until Q1-2012. Bin grid is not to scale.

See also …

ADC research trends: CMOS node adoption

ADC research trends: Migration to CMOS

ADC performance evolution: Thermal noise

ADC performance evolution: Relative noise floor

ADC Survey Data

References

[1] International Technology Roadmap for Semiconductors (ITRS), 2011 Edition [Online]. Available: http://www.itrs.net

[2] B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, pp. 1–4, Nov. 2010.

[3] U. Wismar, D. Wisland, and P. Andreani, “A 0.2V 0.44µW 20 kHz analog to digital ∑∆ modulator with 57 fJ/conversion FoM”, Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Montreux, Switzerland, pp. 187-190, Sept., 2006.