# ADC performance evolution: Walden figure-of-merit (FOM)

Figure 1. Evolution of best reported Walden FOM for delta-sigma modulators (o) and Nyquist ADCs (#). Monotonic state-of-the-art improvement trajectories have been highlighted. Trend fit to DSM (dotted), and Nyquist (dashed) state-of-the-art. Average trend for all designs (dash-dotted) included for comparison.

POWER EFFICIENCY TRENDS: A series of blog posts on A/D-converter performance trends would not be complete without an analysis of figure-of-merit (FOM) trends, would it? We will therefore take a look at the two most commonly used FOM, starting with the by far most popular:

$(1) : F_{A1} = \dfrac{P}{{2}^{ENOB}\times f_{s}}$

where P is the power dissipation, fs is Nyquist sampling rate, and ENOB is the effective number of bits defined by the signal-to-noise and-distortion ratio (SNDR) as:

$(2) : ENOB = \dfrac{SNDR - 1.76}{6.02}$

FA1 is sometimes referred to as the Walden or ISSCC FOM and relates the ADC power dissipation to its performance, represented by sampling rate and conversion error amplitude. The best reported FA1 value each year has been plotted for delta-sigma modulators (DSM) and Nyquist ADCs in Fig. 1. Trajectories for state-of-the-art have been indicated, and trends have been fitted to these state-of-the-art data points. The average improvement trend for all ADCs (2×/2.6 years) is included for comparison.

By dividing the data into DSM and Nyquist subsets, it is seen that delta-sigma modulators have improved their state-of-the-art FOM at an almost constant rate of 2×/2.5 years throughout the existence of the field – just slightly faster than the overall average. State-of-the-art Nyquist ADCs have followed a steeper and more S-shaped evolution path. Their overall trend fits to a 2× improvement every 1.8 years, although it is obvious that evolution rates have changed significantly over time. A more accurate analysis of Nyquist ADC trends should probably make individual fits of the early days glory, the intermediate slowdown, and the recent acceleration phase. This was done in [1] where evolution was analyzed with DSM and Nyquist data merged. However, for simplicity I’ll just stick to the more conservative overall Nyquist trend. [I wouldn’t want anyone to suggest that I’m producing “subjective” or “highly speculative” trend estimates, would I? 😉 ]

Still, if anyone is curious to know … 🙂 … the state-of-the-art data points fit to a 2×/14 months trend between 2000 and 2010. That’s actually faster than Moore’s Law, which is traditionally attributed a 2×/18 months rate [2]-[3]. A new twist on “More than Moore”, perhaps? Even the more conservative overall 2×/21 months trend is close enough to conclude that the state-of-the-art FOM for Nyquist ADCs has developed exponentially in a fashion closely resembling Moore’s Law. And that’s got to be an impressive trend for any analog/mixed circuit performance parameter.

Irrespective of what’s the best fit to data, it should be evident from Fig. 1 that Nyquist ADCs broke away from the overall trend around year 2000, and has since followed a steeper descent in their figures-of-merit. They have also reached further (4.4 fJ) [4] than DSM (35.6 fJ) [5]. The overall trend projects to a 0.2 fJ ADC FOM in 2020. Whether or not that’s possible, we’ll leave for another post. A deeper look at the data also reveals that:

• The acceleration in state-of-the-art is almost completely defined by successive-approximation (SAR) ADCs [4], [6]-[11], accompanied by a single cyclic ADC [12]. The superior energy efficiency of the SAR architecture was empirically shown in [13].
• A significant part of the acceleration can be explained by the increased tendency to leave out, for example I/O power dissipation when reporting experimental results – a trend also observed by Bult [14]. The FOM in the graph was intentionally calculated from the on-chip rather than total power dissipation because: (a) ADCs are increasingly used as a system-on-chip (SoC) building block, which makes the stand-alone I/O power for a prototype irrelevant, and (b) Many authors don’t even report the I/O power anymore.
• FA1 has a bias towards low-power, medium resolution designs rather than high-resolution, and thus benefits from CMOS technology scaling as shown in [15],[16]. An analysis of the underlying data shows that, for the best FA1 every year, the trajectories for ENOB and P follows distinct paths towards consistently lower power and medium resolution. You simply gain more in FA1 by lowering power dissipation than by increasing resolution because (1) does not correctly describe the empirically observed power-resolution tradeoff for ADCs [13],[15].

In order to compare high-resolution ADCs limited by thermal noise, it has therefore been proposed to use a slightly different FOM, sometimes labeled the “Thermal FOM” [17]-[18],

$(3) : F_{B1} = \dfrac{P}{{2}^{2\times ENOB}\times f_{s}}$

This figure-of-merit will be the topic of the next post.

Walden’s survey [19]

#### References

1. B. E. Jonsson, “A survey of A/D-converter performance evolution,” Proc. of IEEE Int. Conf. Electronics Circ. Syst. (ICECS), Athens, Greece, pp. 768–771, Dec., 2010.
2. G.E. Moore, “Cramming more components onto integrated circuits,” Electronics, Vol. 38, No. 8, Apr. 1965.
3. G. E. Moore, “No exponential is forever: but “forever” can be delayed!,” IEEE ISSCC, Dig. Tech. Papers, San Francisco, CA, Feb. 2003, pp. 20–23.
4. M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.
5. J. Xu, X. Wu, M. Zhao, R. Fan, H. Wang, X. Ma, and B. Liu, “Ultra Low-FOM High-Precision ΔΣ Modulators with Fully-Clocked SO and Zero Static Power Quantizers,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.
6. A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS,” IEEE J. Solid-State Circuits, Vol. 47, pp. 1022–1030, Apr., 2012.
7. T.-C. Lu, L.-D. Van, C.-S. Lin, C.-M. Huang, “A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/Conversion-Step SAR ADC for Biomedical Applications,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 1–4, Sept., 2011.
8. S.-K. Lee, S.-J. Park, Y. Suh, H.-J. Park, and J.-Y. Sim, “A 1.3µW 0.6V 8.7-ENOB Successive Approximation ADC in a 0.18µm CMOS,” Symp. VLSI Circ. Digest of Technical Papers, Honolulu, USA, pp. 242–243, June, 2009.
9. H.-C. Hong, and G.-M. Lee, “A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC,” IEEE J. Solid-State Circuits, Vol. 42, pp. 2161–2168, Oct., 2007.
10. M. D. Scott, B. E. Boser, and K. S. J. Pister, “An Ultra-Low Power ADC for Distributed Sensor Networks,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Firenze, Italy, pp. 255–258, Sept., 2002.
11. M. D. Scott, B. E. Boser, and K. S. J. Pister, “An Ultralow-Energy ADC for Smart Dust,” IEEE J. Solid-State Circuits, Vol. 38, pp. 1123–1129, July, 2003.
12. D. Muthers, and R. Tiekert, “A 0.11mm2 low-power A/D-converter cell for 10b 10MS/s operation,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Leuven, Belgium, pp. 251–254, Sept., 2004.
13. B. E. Jonsson, “An empirical approach to finding energy efficient ADC architectures,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011. [PDF @ IMEKO]
14. K. Bult, “Embedded analog-to-digital converters,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Athens, Greece, pp. 52–60, Sept., 2009.
15. B. E. Jonsson, “Using Figures-of-Merit to Evaluate Measured A/D-Converter Performance,” Proc. of 2011 IMEKO IWADC & IEEE ADC Forum, Orvieto, Italy, pp. 1–6, June 2011. [PDF @ IMEKO]
16. B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, Nov. 2010.
17. A. M. A. Ali, C. Dillon, R. Sneed, A. S. Morgan, S. Bardsley, J. Kornblum, and L. Wu, “A 14-bit 125 MS/s IF/RF sampling pipelined ADC with 100 dB SFDR and 50 fs jitter,” IEEE J. Solid-State Circuits, Vol. 41, pp. 1846–1855, Aug, 2006.
18. C. Wulff, and T. Ytterdal, “Design of a 7-bit, 200MS/s, 2mW pipelined ADC with switched open-loop amplifiers in a 65nm CMOS technology,” Proc. of NORCHIP, Aalborg, Denmark, Nov., 2007.
19. R. Walden, “Analog-to-digital conversion in the early twenty-first century,” Wiley Encyclopedia of Computer Science and Engineering, pp. 126–138, Wiley, 2008.

### 14 responses to “ADC performance evolution: Walden figure-of-merit (FOM)”

1. Steven Hardy

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2. george storm

Maybe I’m naive, but I would expect the Walden FOM to track logic switching energy right up to the point that kT noise becomes important.
This is in the absence of architectural improvements – and surprisingly it looks as if the ‘more mature’ Nyquist converters have seen significant improvements (realtive to Walden) even over the last ten years.
So the question comes down to the folllowing: do we expect logic power densities to cotinue to improve at the same rate, and do we anticipate further architectural optimisation.
My answer would be that logic looks “safe” for at least another three generations, and that i haven’t the faintest idea about architectures.

I would however like here to repeat my reservation about thes graphs as a mode of comparison between SARs and DSM: if we remove (synthetic?) normalisation features, the FOM for high-order DSMs increases as the signal bandwidh reduces as a proportion of sample rate. High-order DSMs are already challenging, so I wouldn’t wish to see FOMs divert effort from work on high-resolution DSM design.

• As I said at the end of the post, this FOM does not correctly describe the power-resolution tradeoff for ADCs limited by thermal noise (including many DSM and SAR), and in the next post I will show the evolution for the thermal FOM, which does it almost perfectly. So, you’ll have to wait for that one.

• It isn’t obvious to me why, below kT/C noise, this FOM would universally always track the logic switching energy. As I understand, it would only do so for architectures and spec ranges where logic is the single dominant power dissipator and the number of gates grows as 2^N (which it does not for many architectures, e.g., for typical 1 and 1.5-b pipeline ADCs where it’s more proportional to N).

There are also other potential power contributors, such as on-chip clock- and reference generators which aren’t obviously below the logic energy limit. Pelgrom, I believe, has treated matching limits to power dissipation.

All of these could make the FOM evolution “un-track” that of logic energy.

3. Reblogged this on Nirav Desai's Blog.

4. Oliver Lin

I think a little more explanation should be given to the “Thermal noise limited FOM” and traditional Walden FOM. As I understand it, Thermal noise limited FOM uses 2^(2ENOB) because we can imagine 2 identical ADCs sample same signal and then doing average to get output. The noise is only reduced by 3dB by averaging (ENOB increased by 0.5b) by consuming 2x power from 2 ADCs. Therefore it is easy to understand 2x power can exchange for 3db noise improvement. What confused me is the traditional Walden FOM: Even if quantization noise is dominant, how can we exchange 2x power with 6 db noise reduction?

5. Oliver Lin

May be we can explain it as 2^ENOB is dominant by quantization noise but 2x power can make it 2x faster? Imagine 2 ADC samples the output with frequency fs but has a delay of Ts/2. Then the output is combined. In this case the fs is actual 2x of original one so that we used 2x power to exchange 2x fs. It makes perfect sense!

The thermal FOM is “explained” (or justified) a little bit more in the subsequent post where its trends are treated. My explanation – or rather the sources I refer to – tend to focus on kT/C-noise in the S/H as the fundamental limit. The special case you mention – where the design “tweak” is to double the hardware and average the thermal noise – gives an intuitive alternate explanation. For more theory, I’d recommend the works by Sundström et al and Zhang et al. (references 15 and 16 in this post)
I’ll comment on the Walden FOM separately.

• First a short one: I think the latter would make just as much sense also when thermal noise the dominant noise source.

• This one’s a bit longer: Your comments open up for a lot of interesting discussions. First of all: What do we mean by “explaining” a FOM? As touched upon in this paper, many FOM have been proposed (with various justifications), but few of them align well with any significant range of empirical data. I.e., most of them can’t be empirically justified as far as I can tell.

Remains to explain what the FOM was intended to capture, or what it is “trying to tell us”. I feel that your examples are approaching this.

When it comes to the “Walden” FOM, I’m not sure what the original intentions were. Long before Walden’s famous paper, a very similar FOM was proposed by Emmert et al. (ref [3] here). My best guess is that their FOM (which used N rather than ENOB) should capture the doubling of Flash ADC hardware for every nominal bit of resolution. At the 6-b they were working on, maybe nothing was limited by thermal noise anyway, so it made reasonable sense for the comparison with state-of-the-art that they were trying to do.

[If any of the authors – Günter Emmert, Emil Navratil, Franz Parzefall or Peter Rydval are able to share your thoughts with us, you’re most welcome.]

With the Walden paper(s), this FOM (first with “SNR-bits”, later with ENOB) took off on a much larger scale, and has eventually reached nearly canonical status. Again, I can only speculate why Walden proposed this particular FOM. As far as I can tell, there is neither any significant theoretical nor empirical justification of its introduction. Perhaps it was considered common knowledge at the time.

What I do know, however, is that the empirical data reported in the early years would look more like a 2^ENOB energy limit. Today when P/fs has been extremely optimized in scientific ADCs, just about everything on chip is pushed into its thermal-noise power limit, and therefore the state-of-the-art bound is almost exactly proportional to 4^ENOB as shown here. I’m planning to illustrate this trend-shift over time in a future post. (EDIT: Now I’ve done that here.)

With the collective body of empirical results available today, my opinion is that the Walden FOM can no longer play the role of a FOM for universal performance comparison over any broader range of ENOB. See this paper for what I believe is a good explanation of why. My impression is that authors are now increasingly reporting the Thermal FOM or the Schrier FOM as a complement to the Walden FOM, and I believe that trend will continue until the Walden FOM is phased-out.

Now, back to your second example: What you describe is of course “time-interleaving without any power penalty for doubling the input bandwidth”. This special-case is captured perfectly by the Walden FOM. Does that “prove” or justify the Walden FOM as a universal performance comparator? Does it help us to “understand” it? Not really. It just happens to match this special case where we take integer steps along the P and fs axes in design space, and the steps are themselves restricted to only constitute multiplications of identical hardware – never a design tweak.

To justify, or explain a FOM we need to verify that it matches the theoretical and/or empirical performance bounds when its parameters {P, fs, ENOB} can move freely. Since the Walden FOM only matches empirical bounds in special cases, I believe there is no way to really understand it – only where it came from, and why it was originally introduced.

But some of that are simply my opinions. Even if I believe they are firmly founded in the survey data, I may be wrong. Therefore it’s interesting to hear if anyone has alternate opinions/explanations.