ADC performance evolution: Relative noise floor


Figure 1. Evolution of relative noise-floor for DSM (o) and Nyquist (#) ADCs over time.

WHAT YOU SEE IS WHAT YOU GET: We have previously studied the evolution of absolute thermal noise levels, and sampling jitter for analog-to-digital converters (ADC). Finally, the overall noise performance evolution is observed with all noise contributors included. Whereas the two previous posts analyzed two fundamental noise components in isolation, this post looks at the actual noise performance achieved with everything included. This is the ADC performance you actually get.

Observation of ADC noise floor trends

The ADC survey data spans a very wide range of converter specifications. An SNR of x dB in 20 kHz bandwidth is not as impressive as achieving the same in a 1GHz band. Using the relative noise-floor nr in dB/Hz derived by (1) allow ADCs with widely different Nyquist bandwidths (BW) to be compared with respect to noise performance.

(1) : n_{r}= - ( SNR+10\times\log_{10}BW )

Figure 1 shows the evolution of nr for delta-sigma modulators (DSM) and Nyquist ADCs over time. A similar plot, based on less data, and not differentiating between DSM and Nyquist ADCs is found in [1]. From a linear fit of the state-of-the-art data points, it is seen here that ADC noise-floor for has evolved at an average rate of ~2.2 dB/year until year 2000 for DSM, after which it has remained in saturation. Nyquist ADCs have developed at a slower rate of ~1.3 dB/year until 2010. The current state-of-the-art is approximately the same for both: –162 dB/Hz for DSM [2], and –161 dB/Hz for Nyquist [3]. Since the state-of-the-art for Nyquist converters was so recently reported, it cannot be concluded only from Fig. 1 that the noise floor for Nyquist ADCs is in saturation. A likely explanation for the DSM trend is, however, the lower signal swing, and thus higher relative noise-floor, implied by the continuous scaling of semiconductor technology [4],[5]. This is also seen in Fig. 2. Although the absolute noise-floor may remain constant in devices [6], the relative noise-floor is raised when signal swing is reduced. New technologies may allow higher bandwidths, but the simultaneous combination of SNR and bandwidth has not improved for a decade due to this inherent dynamic-range limitation of nanometer technology [5]. It is likely to assume that Nyquist converters will suffer from this limit at least as much as delta-sigma modulators do. Noise-performance normalized to signal bandwidth therefore seems to have reached the physical limits of process technology defined by the available signal swing. Expecting a further reduction in signal swing [9], future ADCs could very well fail to maintain the current state-of-the-art in noise performance.

Figure 2. Evolution of relative noise-floor for DSM (o) and Nyquist (#) ADCs vs. node geometry (any technology).

Conclusion: ADC noise performance trends

Over the last three posts, it was seen that the overall state-of-the-art with respect to absolute noise power, sampling jitter, and relative total noise floor has not improved during the last 5–10 years. It is therefore concluded that all significant aspects of ADC noise performance appear to have reached saturation. This is an expected, yet significant result of the study as it clearly confirms the commonly raised concerns regarding analog design and dynamic range in scaled technologies, e.g., in [4]-[8].

My conclusion is that A/D-converters have already hit the noise floor – at least its softer upper coating.

What do you conclude?

In upcoming parts of the ADC performance evolution series of posts we will next take a look at ADC linearity trends.

Additional remarks

  • As commented in part 1, the trends of degradation observed below 65 nm in Fig. 2 may be due to lack of reported attempts, and not necessarily due to physics.
  • Using a circuit design that allows for large input signal swing can help a lot in improving relative noise floor performance. As an example, the state-of-the-art design by Hurrell et al. [3] reports an 8.2 V peak-to-peak input full-scale range.

See also …

ADC performance evolution: Thermal noise

ADC performance evolution: Jitter

ADC performance evolution: Low-voltage operation – part 1

ADC performance evolution: Low-voltage operation – part 2

ADC survey data

References

  1. B. E. Jonsson, “A survey of A/D-converter performance evolution,” Proc. of IEEE Int. Conf. Electronics Circ. Syst. (ICECS), Athens, Greece, pp. 768–771, Dec., 2010.
  2. R. Naiknaware, and T. Fiez, “142dB ∆∑ ADC with a 100nV LSB in a 3V CMOS Process,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), Orlando, USA, pp. 5-8, May, 2000.
  3. C. P. Hurrell, C. Lyden, D. Laing, D. Hummerston, and M. Vickery, “An 18 b 12.5 MS/s ADC With 93 dB SNR,” IEEE J. Solid-State Circuits, Vol. 45, pp. 2647-2654, Dec., 2010.
  4. K. Bult, “Analog design in deep sub-micron CMOS,” Proc. of Eur. Solid-State Circ. Conf. (ESSCIRC), Stockholm, Sweden, pp. 126–132, Sept., 2000.
  5. B. E. Jonsson, “On CMOS scaling and A/D-converter performance,” Proc. of NORCHIP, Tampere, Finland, Nov. 2010.
  6. W. Sansen, “Analog design challenges in nanometer CMOS technologies,” Proc. of IEEE Asian Solid-State Circ. Conf. (ASSCC), Jeju, Korea, pp. 5–9, Nov., 2007.
  7. B. Murmann, “A/D converter trends: Power dissipation, scaling and digitally assisted architectures,” Proc. of IEEE Custom Integrated Circ. Conf. (CICC), San Jose, California, USA, pp. 105–112, Sept., 2008.
  8. Y. Chiu, B. Nicolic, and P. R. Gray, “Scaling of analog-to-digital converters into ultra-deep-submicron CMOS,” in Proc. Custom Integrated Circuits Conf., San Jose, Sept. 2005, pp. 375–382.
  9. International Technology Roadmap for Semiconductors (ITRS), 2011 Edition [Online]. Available: http://www.itrs.net
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7 responses to “ADC performance evolution: Relative noise floor

  1. Pingback: ADC performance evolution: Jitter | Converter Passion

  2. Pingback: ADC performance evolution: Thermal noise | Converter Passion

  3. I thought comparative analysis of delta-sigma performance was more complex than this implies – maybe it’s a case of hidden tools?

    I can see metallisation presenting a fundamental limit to speed, although monolithic 3D and/or new conductor technologies may move the bar over time. An issue that affects ultimate accuracy could be errors created via time-varying device dissipation – which could mean that total converter area no longer shrinks with geometry. However, it may turn out that other existing limits are addressed by the use of fully depleted channels (FDSOI/FINFET), so perhaps we’ll see some improvement for a period.
    N.B. that non-systematic errors can be statistically averaged by using multiple A/D converters for the same signal.

  4. Pingback: ADC performance evolution: Low-voltage operation – part 1 | Converter Passion

  5. Pingback: ADC performance evolution: Linearity (SFDR) | Converter Passion

  6. Pingback: ADC performance evolution: Sampling rate and resolution | Converter Passion

  7. Pingback: ADC performance evolution: Thermal figure-of-merit (FOM) | Converter Passion

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